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IDT72T36135ML6BBGI Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT72T36135ML6BBGI Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 48 page  COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36 7 MAY 29, 2006 PIN DESCRIPTION (CONTINUED) Symbol Name I/O TYPE Description RCLK/ Read Clock/ HSTL-LVTTL port has been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. RD Read Strobe INPUT REN should be tied LOW. RCS Read Chip Select HSTL-LVTTL RCSprovidessynchronouscontrolofthereadportandoutputimpedanceofQn,synchronoustoRCLK.During INPUT a Master Reset or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance regardless of RCS. REN Read Enable HSTL-LVTTL If Synchronous operation of the read port has been selected, REN enablesRCLK for reading data from the INPUT FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the REN input should be tied LOW. RHSTL(1) Read Port HSTL LVTTL This pin is used to select HSTL or 2.5v LVTTL outputs for the FIFO. If HSTL inputs are required, this input Select INPUT must be tied HIGH. Otherwise it should be tied LOW. RT Retransmit HSTL-LVTTL RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF[1:2] flag to LOW INPUT ( OR[1:2]toHIGHinFWFTmode)anddoesn’tdisturbthewritepointer,programmingmethod,existingtiming mode or programmable flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump to the ‘mark’ location. SCLK Serial Clock HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that INPUT SEN is enabled. SEN Serial Enable HSTL-LVTTL SENenablesserialloadingofprogrammableflagoffsets. INPUT SHSTL System HSTL LVTTL All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input. Select INPUT TCK(2) JTAG Clock HSTL-LVTTL Clock input for JTAG function. TMS and TDI are sampled on the rising edge of TCK. Data is output on INPUT TDO on the falling edge. TRST(2) JTAG Reset HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. INPUT TMS JTAG Mode HSTL-LVTTL TMS is a serial input pin. Bits are serially loaded on the rising edge of TCK, which selects 1 of 5 modes of Select INPUT operation for the JTAG boundary scan. TDI Test Data Input HSTL-LVTTL During JTAG boundary scan operation test data is serially loaded via TDI on the rising edge of TCK. INPUT This is also the data for the Instruction Register, ID Register and Bypass Register. TDO TestDataOutput HSTL-LVTTL During JTAG boundary scan operation test data is serially output via TDO on the falling edge of TCK. OUTPUT This output is in High-Z except when shifting, while in SHIFT-DR and SHIFT-IR controller states. WEN WriteEnable HSTL-LVTTL When Synchronous operation of the write port has been selected, WEN enables WCLK for writing data into INPUT theFIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the WEN input should be tied LOW. WCS WriteChipSelect HSTL-LVTTL This pin disables the write port data inputs when the device write port is configured for HSTL mode. This INPUT provides added power savings. WCLK/ WriteClock/ HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WR WriteStrobe INPUT WCLK writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into the FIFO on a rising edge in an Asynchronous manner, ( WEN should be tied to its active state). WHSTL(1) Write Port HSTL LVTTL This pin is used to select HSTL or 2.5V LVTTL inputs for the FIFO. If HSTL inputs are required, this input must Select INPUT be tied HIGH. Otherwise it should be tied LOW. Vcc +2.5v Supply Power These are Vcc supply inputs and must be connected to the 2.5V supply rail. GND Ground Pin GND These are Ground pins an dmust be connected to the GND rail. Vref Reference I This is a Voltage Reference input and must be connected to a voltage level determined from the table, Voltage “Recommended DC Operating Conditions”. This provides the reference voltage when using HSTL class inputs. If HSTL class inputs are not being used, this pin should be tied LOW. VDDQ O/P Rail Voltage I This pin should be tied to the desired voltage rail for providing power to the output drivers. NOTES: 1. Inputs should not change state after Master Reset. 2. If the JTAG feature is not being used, TCK and TRST should be tied LOW. |
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