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CY7C1350G
Document #: 38-05524 Rev. *F
Page 8 of 15
ISB3
Automatic CE
Power-Down
Current—CMOS
Inputs
VDD = Max, Device Deselected, or
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
4-ns cycle, 250 MHz
105
mA
5-ns cycle, 200 MHz
95
mA
6-ns cycle, 166 MHz
85
mA
7.5-ns cycle, 133 MHz
75
mA
10-ns cycle, 100 MHz
65
mA
ISB4
Automatic CE
Power-Down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
All speeds
45
mA
Capacitance[12]
Parameter
Description
Test Conditions
100 TQFP
Max.
119 BGA
Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VDD = 3.3V, VDDQ = 3.3V
55
pF
CCLK
Clock Input Capacitance
5
5
pF
CI/O
Input/Output Capacitance
5
7
pF
Thermal Resistance[12]
Parameter
Description
Test Conditions
100 TQFP
Package
119 BGA
Package
Unit
Θ
JA
Thermal Resistance (Junction to
Ambient)
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA/JESD51.
30.32
34.1
°C/W
Θ
JC
Thermal Resistance (Junction to
Case)
6.85
14.0
°C/W
Electrical Characteristics Over the Operating Range[10, 11] (continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
AC Test Loads and Waveforms
Note:
12. Tested initially and after any design or process changes that may affect these parameters.
OUTPUT
R = 317
Ω
R = 351
Ω
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
RL = 50Ω
Z0 = 50Ω
VT = 1.5V
3.3V
ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
≤ 1 ns
≤ 1 ns
(c)
OUTPUT
R = 1667
Ω
R =1538
Ω
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
RL = 50Ω
Z0 = 50Ω
VT = 1.25V
2.5V
ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
≤ 1 ns
≤ 1 ns
(c)
3.3V I/O Test Load
2.5V I/O Test Load
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