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P4C1026-25J4MB Datasheet(PDF) 5 Page - Pyramid Semiconductor Corporation |
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P4C1026-25J4MB Datasheet(HTML) 5 Page - Pyramid Semiconductor Corporation |
5 / 10 page P4C1026 Page 5 of10 Document # SRAM127 REV E TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE WE WE WE WE CONTROLLED)(10,11) Notes: 10. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show t WZ and tOW. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state 13. Write Cycle Time is measured from the last valid address to the first transitioning address. TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7) AC CHARACTERISTICS - WRITE CYCLE (V CC = 5V ± 10%, All Temperature Ranges) (2) Sym. Parameter -15 -20 -25 -35 Unit Min Min Min Min Max Max Max Max t WC t CW t AW t AS t WP t AH t DW t DH t WZ t DW Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time from End of Write Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 13 12 12 0 12 0 7 0 2 6 20 15 15 0 15 0 8 0 2 8 25 18 18 0 18 0 10 0 2 35 25 25 0 25 0 15 0 3 15 ns ns ns ns ns ns ns ns ns ns 10 |
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