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PM5357-BI Datasheet(PDF) 7 Page - PMC-Sierra, Inc |
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PM5357-BI Datasheet(HTML) 7 Page - PMC-Sierra, Inc |
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7 / 432 page  PRODUCTION S/UNI-622-POS PMC-Sierra, Inc. PM5357 S/UNI-622-POS DATASHEET PMC-1980911 ISSUE 5 SATURN USER NETWORK INTERFACE (622-POS) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 2 10.4 THE RECEIVE APS, SYNCHRONIZATION EXTRACTOR AND BIT ERROR MONITOR (RASE) ........................................................................................................................... 69 10.5 RECEIVE PATH OVERHEAD PROCESSOR (RPOP).................................................... 70 10.6 RECEIVE ATM CELL PROCESSOR (RXCP) ................................................................. 75 10.7 RECEIVE POS FRAME PROCESSOR (RXFP) ............................................................. 79 10.8 TRANSMIT LINE INTERFACE (CSPI-622) .................................................................... 82 10.9 TRANSMIT SECTION OVERHEAD PROCESSOR (TSOP)........................................... 83 10.10 TRANSMIT LINE OVERHEAD PROCESSOR (TLOP) ................................................... 84 10.11 TRANSMIT PATH OVERHEAD PROCESSOR (TPOP) ................................................. 85 10.12 TRANSMIT ATM CELL PROCESSOR (TXCP)............................................................... 86 10.13 TRANSMIT POS FRAME PROCESSOR (TXFP) ........................................................... 87 10.14 SONET/SDH PATH TRACE BUFFER (SPTB)................................................................ 90 10.15 SONET/SDH SECTION TRACE BUFFER (SSTB)......................................................... 92 10.16 ATM UTOPIA AND PACKET OVER SONET/SDH POS-PHY SYSTEM INTERFACES .. 94 10.17 WAN SYNCHRONIZATION CONTROLLER (WANS)..................................................... 98 10.18 JTAG TEST ACCESS PORT ........................................................................................ 101 10.19 MICROPROCESSOR INTERFACE.............................................................................. 101 11 NORMAL MODE REGISTER DESCRIPTION ............................................................................ 109 12 TEST FEATURES DESCRIPTION.............................................................................................. 336 12.1 MASTER TEST AND TEST CONFIGURATION REGISTERS ...................................... 336 12.2 JTAG TEST PORT........................................................................................................ 339 13 OPERATION ............................................................................................................................... 346 13.1 SONET/SDH FRAME MAPPINGS AND OVERHEAD BYTE USAGE .......................... 346 13.2 ATM CELL DATA STRUCTURE.................................................................................... 352 13.3 PACKET OVER SONET/SDH DATA STRUCTURE...................................................... 353 13.4 SETTING ATM MODE OF OPERATION....................................................................... 355 13.5 SETTING PACKET-OVER-SONET/SDH MODE OF OPERATION .............................. 356 13.6 SETTING SONET OR SDH MODE OF OPERATION................................................... 357 13.7 BIT ERROR RATE MONITOR ...................................................................................... 358 13.8 AUTO ALARM CONTROL CONFIGURATION.............................................................. 359 13.9 CLOCKING OPTIONS.................................................................................................. 360 13.10 WAN SYNCHRONIZATION (WANS BLOCK) ............................................................... 361 |
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