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P4C149-55DMB Datasheet(PDF) 5 Page - Pyramid Semiconductor Corporation |
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P4C149-55DMB Datasheet(HTML) 5 Page - Pyramid Semiconductor Corporation |
5 / 10 page P4C148/P4C149 Page 5 of 10 Document # SRAM104 REV B Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figures 1 and 2 Mode CE CE CE CE CE WE WE WE WE WE Output Power Standby H X High Z Standby Read L H D OUT Active Write L L High Z Active AC TEST CONDITIONS TRUTH TABLE Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Due to the ultra-high speed of the P4C148/149, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the V CC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between V CC and ground. To avoid signal reflections, proper termination must be used; for example, a 50 Ω test environment should be terminated into a 50 Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116 Ω resistor must be used in series with D OUT to match 166Ω (Thevenin Resistance). |
Similar Part No. - P4C149-55DMB |
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Similar Description - P4C149-55DMB |
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