P4C1258

Page 5 of 9

Document # SRAM123 REV OR

12. Transition is measured ±200mV from steady state voltage prior to

change with specified loading in Figure 1. This parameter is

sampled and not 100% tested.

Notes:

9. CE and WE must be LOW for WRITE cycle.

10. If CE goes HIGH simultaneously with WE HIGH, the output remains

in a high impedance state.

11. Write Cycle Time is measured from the last valid address to the first

transition address.

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE

WE

WE

WE

AC CHARACTERISTICS - WRITE CYCLE

(V

(2)

Sym.

Parameter

-15

-20

-25

-35

Unit

Min

Min

Min

Min

Max

Max

Max

Max

t

WC

t

CW

t

AW

t

AS

t

WP

t

AH

t

DW

t

DH

t

WZ

t

DW

Write Cycle Time

Chip Enable Time to End of Write

Address Valid to End of Write

Address Set-up Time

Write Pulse Width

Address Hold Time from End of Write

Data Valid to End of Write

Data Hold Time

Write Enable to Output in High Z

Output Active from End of Write

13

12

12

0

12

0

7

0

2

6

20

15

15

0

15

0

8

0

2

8

25

18

18

0

18

0

10

0

2

35

25

25

0

25

0

15

0

3

15

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

10