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CY7C1150V18-333BZXC Datasheet(PDF) 11 Page - Cypress Semiconductor

Part # CY7C1150V18-333BZXC
Description  18-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1150V18-333BZXC Datasheet(HTML) 11 Page - Cypress Semiconductor

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CY7C1146V18
CY7C1157V18
CY7C1148V18
CY7C1150V18
Document Number: 001-06621 Rev. *C
Page 11 of 27
The write cycle descriptions of CY7C1148V18 follows, [3, 9]
BWS0 BWS1 BWS2 BWS3
KK
Comments
LLLL
L – H
When the Data portion of a write sequence is active, all four bytes (D[35:0]) are
written into the device.
LLLL
L – H When the Data portion of a write sequence is active, all four bytes (D[35:0]) are
written into the device.
L
H
H
H
L – H
When the Data portion of a write sequence is active, only the lower byte (D[8:0]) is
written into the device. D[35:9] remains unaltered.
L
H
H
H
L – H When the Data portion of a write sequence is active, only the lower byte (D[8:0]) is
written into the device. D[35:9] remains unaltered.
H
L
H
H
L – H
When the Data portion of a write sequence is active, only the byte (D[17:9]) is written
into the device. D[8:0] and D[35:18] remains unaltered.
H
L
H
H
L – H When the Data portion of a write sequence is active, only the byte (D[17:9]) is written
into the device. D[8:0] and D[35:18] remains unaltered.
H
H
L
H
L – H
When the Data portion of a write sequence is active, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] remains unaltered.
H
H
L
H
L – H When the Data portion of a Write sequence is active, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] remains unaltered.
H
H
H
L
L – H
When the Data portion of a write sequence is active, only the byte (D[35:27]) is
written into the device. D[26:0] remains unaltered.
H
H
H
L
L – H When the Data portion of a write sequence is active, only the byte (D[35:27]) is
written into the device. D[26:0] remains unaltered.
HHHH
L – H
No data is written into the device when this portion of a write operation is active.
HHHH
L – H No data is written into the device when this portion of a write operation is active.


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