PRELIMINARY
16-Mbit (2M x 8) Static RAM
CY7C1069DV33
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-05478 Rev. *C
Revised September 14, 2006
Features
•High speed
—tAA = 10 ns
• Low active power
—ICC = 125 mA @ 10 ns
• Low CMOS standby power
—ISB2 = 25 mA
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
• Available in Pb-free 54-pin TSOP II package and 48-ball
VFBGA packages
Functional Description
The CY7C1069DV33 is a high-performance CMOS Static
RAM organized as 2,097,152 words by 8 bits. Writing to the
device is accomplished by enabling the chip (by taking CE1
LOW and CE2 HIGH) and Write Enable (WE) inputs LOW.
Reading from the device is accomplished by enabling the chip
(CE1 LOW and CE2 HIGH) as well as forcing the Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
See the truth table at the back of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a Write operation (CE1 LOW, CE2 HIGH, and WE
LOW).
The CY7C1069DV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-ball very fine-pitch ball grid array (VFBGA) package.
Selection Guide
–10
Unit
Maximum Access Time
10
ns
Maximum Operating Current
125
mA
Maximum CMOS Standby Current
25
mA
Logic Block Diagram
Pin Configuration
Top View
TSOP II
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
43
42
16
15
29
30
A5
A6
A7
A8
A0
A1
OE
VSS
A17
I/O7
A2
CE1
I/O0
I/O1
A3
A4
18
17
20
19
27
28
25
26
22
21
23
24
I/O2
I/O3
A16
A15
VCC
I/O6
NC
I/O5
I/O4
A14
A13
A12
A11
A9
A10
CE2
44
46
45
47
50
49
48
51
53
52
54
VSS
VCC
A19
A18
VCC
VCC
VSS
NC
VSS
NC
VCC
VSS
NC
NC
NC
NC
NC
NC
NC
NC
A20
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
INPUT BUFFER
2M x 8
ARRAY
A0
I/O0–I/O7
OE
CE2
WE
CE1
A9
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