PRELIMINARY
CY7C1062DV33
Document #: 38-05477 Rev.*C
Page 4 of 10
AC Switching Characteristics Over the Operating Range[5]
Parameter
Description
–10
Unit
Min.
Max.
Read Cycle
tpower
VCC (typical) to the first access
[6]
100
µs
tRC
Read Cycle Time
10
ns
tAA
Address to Data Valid
10
ns
tOHA
Data Hold from Address Change
3
ns
tACE
CE active LOW to Data Valid[7]
10
ns
tDOE
OE LOW to Data Valid
5
ns
tLZOE
OE LOW to Low-Z[8]
1
ns
tHZOE
OE HIGH to High-Z[8]
5
ns
tLZCE
CE active LOW to Low-Z[7, 8]
3
ns
tHZCE
CE deselect HIGH to High-Z[7, 8]
5
ns
tPU
CE active LOW to Power-up[7, 9]
0
ns
tPD
CE deselect HIGH to Power-down[7, 9]
10
ns
tDBE
Byte Enable to Data Valid
5
ns
tLZBE
Byte Enable to Low-Z[8]
1
ns
tHZBE
Byte Disable to High-Z[8]
5
ns
Write Cycle[10, 11]
tWC
Write Cycle Time
10
ns
tSCE
CE active LOW LOW to Write End[7]
7
ns
tAW
Address Set-up to Write End
7
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
7
ns
tSD
Data Set-up to Write End
5.5
ns
tHD
Data Hold from Write End
0
ns
tLZWE
WE HIGH to Low-Z[8]
3
ns
tHZWE
WE LOW to High-Z[8]
5
ns
tBW
Byte Enable to End of Write
7
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
output loading as shown in (a) of AC Test Loads, unless specified otherwise.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 and CE2 and CE3 LOW. When deselect HIGH, CE indicates the
CE1 or CE2 or CE3 HIGH
8. tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±
200 mV from steady-state voltage.
9. These parameters are guaranteed by design and are not tested.
10. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 LOW, CE3 LOW and WE LOW. The chip enables must be active and WE must
be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the
leading edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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