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ICS95V857CGLF-T Datasheet(PDF) 6 Page - Integrated Circuit Systems |
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ICS95V857CGLF-T Datasheet(HTML) 6 Page - Integrated Circuit Systems |
6 / 13 page 6 ICS95V857C 1190A—12/16/05 Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, where the cycle (tc) decreases as the frequency goes up. 3. Switching characteristics guaranteed for application frequency range. 4. Static phase offset shifted by design. Timing Requirements TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Max clock frequency freqop 2.5V+0.2V @ 25 oC 45 233 MHz Application Frequency Range freqApp 2.5V+0.2V @ 25 oC 95 220 MHz Input clock duty cycle dtin 40 60 % CLK stabilization TSTAB 15 µs Switching Characteristics (see note 3) PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS Low-to high level propagation delay time tPLH 1 CLK_IN to any output 3.5 ns High-to low level propagation delay time tPLL 1 CLK_IN to any output 3.5 ns Output enable time tEN PD# to any output 3 ns Output disable time tdis PD# to any output 3 ns Period jitter Tjit (per) 100MHz to 200MHz -30 30 ps Half-period jitter t(jit_hper) 100MHz to 200MHz -75 75 ps Input clock slew rate tsl(i) 14 V/ns Output clock slew rate tsl(o) 12 V/ns Cycle to Cycle Jitter 1 Tcyc-Tcyc 100MHz to 200MHz -50 50 ps Static Phase Offset t(static phase offset) 4 -50 0 50 ps Output to Output Skew Tskew 40 ps |
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