5 / 10 page
CY7C1021BN
CY7C10211BN
Document #: 001-06494 Rev. *A
Page 5 of 10
Write Cycle[8]
tWC
Write Cycle Time
10
12
15
ns
tSCE
CE LOW to Write End
8
9
10
ns
tAW
Address Set-Up to Write End
7
8
10
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tSD
Data Set-Up to Write End
5
6
8
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z[6]
33
3
ns
tHZWE
WE LOW to High Z[6, 7]
56
7
ns
tBW
Byte Enable to End of Write
7
8
9
ns
Switching Waveforms
Read Cycle No. 1[9, 10]
Read Cycle No. 2 (OE Controlled)[10, 11]
Notes:
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a
write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that
terminates the write.
9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
10. WE is HIGH for read cycle.
Switching Characteristics[5] Over the Operating Range (continued)
Parameter
Description
7C10211B-10
7C1021B-12
7C1021B-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
HIGH
ICC
ISB
IMPEDANCE
DATA
tDBE
tLZBE
tHZCE
ICC
ISB
ADDRESS
OE
CE
BHE,BLE
OUT
VCC
SUPPLY
CURRENT
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