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P4C150-20FMB Datasheet(PDF) 6 Page - Pyramid Semiconductor Corporation |
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P4C150-20FMB Datasheet(HTML) 6 Page - Pyramid Semiconductor Corporation |
6 / 11 page P4C150 Page 6 of 11 Document # SRAM105 REV A Mode CS CS CS CS CS Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figures 1 and 2 AC TEST CONDITIONS Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Not Selected RESET Output Disabled READ WRITE RS RS RS RS RS X L H H H H L L L L OE OE OE OE OE X X H L X TRUTH TABLE WE WE WE WE WE X H H H L Output High Z High Z High Z D OUT High Z Note: Due to the ultra-high speed of the P4C150, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the V CC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between V CC and ground. To avoid signal reflections, proper termination must be used; for example, a 50 Ω test environment should be terminated into a 50 Ω loadwith1.73V(TheveninVoltage)atthecomparatorinput,and a 116 Ω resistormustbeusedinserieswithD OUT to match 166Ω (Thevenin Resistance). |
Similar Part No. - P4C150-20FMB |
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Similar Description - P4C150-20FMB |
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