512K (32K x 16) Static RAM
CY7C1020DV33
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-05461 Rev. *D
Revised November 8, 2006
Features
• Pin-and function-compatible with CY7C1020CV33
• High speed
—tAA = 10 ns
• Low active power
—ICC = 60 mA @ 10 ns
• Low CMOS standby power
—ISB2 = 3 mA
• 2.0V Data retention
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Independent control of upper and lower bits
• Available in Pb-free 44-pin 400-Mil wide Molded SOJ and
44-pin TSOP II packages
Functional Description[1]
The CY7C1020DV33 is a high-performance CMOS static
RAM organized as 32,768 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A14). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A14).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020DV33 is available in Pb-free 44-pin 400-Mil
wide Molded SOJ and 44-pin TSOP II packages.
Logic Block Diagram
Pin Configuration[2]
1
2
3
4
5
6
7
8
9
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A5
18
17
20
19
27
28
25
26
22
21
23
24
Top View
A6
A7
NC
A3
A2
A1
A0
A14
A4
A8
A9
A10
A11
A12
A13
NC
NC
OE
BHE
BLE
CE
WE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
VCC
VCC
VSS
VSS
NC
10
32K x 16
RAM Array
I/O0–I/O7
A7
A6
A5
A4
A3
A0
COLUMN DECODER
DATA IN DRIVERS
OE
A2
A1
I/O8–I/O15
CE
WE
BLE
BHE
SOJ/TSOP II
Notes
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com
2. NC pins are not connected on the die.
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