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STAC9753A Datasheet(PDF) 2 Page - Integrated Device Technology |
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2 / 106 page STAC9752A/9753A AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK PC AUDIO IDT™ 2 STAC9752A/9753A V 1.5 1206 AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK TABLE OF CONTENTS 1. PRODUCT BRIEF ...................................................................................................................... 6 1.1. Features ............................................................................................................................................ 6 1.2. Description ........................................................................................................................................ 6 1.3. STAC9752A/9753A Block Diagram ................................................................................................... 8 1.4. Key Specifications ............................................................................................................................. 9 1.5. Related Materials .............................................................................................................................. 9 1.6. Additional Support ............................................................................................................................. 9 2. CHARACTERISTICS AND SPECIFICATIONS .......................................................................10 2.1. Electrical Specifications ................................................................................................................... 10 2.2. AC Timing Characteristics ............................................................................................................... 16 3. TYPICAL CONNECTION AND POWER DIAGRAMS .............................................................21 3.1. STAC9752A/9753A Typical Connection Diagram for 48-pin LQFP ................................................ 21 3.2. STAC9752A/9753A Typical Connection Diagram for 32-pad QFN ................................................. 22 3.3. Split Independent Power Supply Operation .................................................................................... 23 3.4. Split Independent Power Supply Operation for the 32-pad QFP Package ......................................24 4. CONTROLLER, CODEC, AND AC-LINK ................................................................................25 4.1. AC-Link Physical interface ............................................................................................................... 25 4.2. Controller to Single CODEC ............................................................................................................ 25 4.3. Controller to Multiple CODECs ........................................................................................................ 26 4.4. Clocking for Multiple CODEC Implementations ............................................................................... 27 4.5. STAC9752A/9753A as a Primary CODEC ...................................................................................... 28 4.6. AC-Link Power Management ........................................................................................................... 28 5. AC-LINK DIGITAL INTERFACE ..............................................................................................31 5.1. Overview ......................................................................................................................................... 31 5.2. AC-Link Serial Interface Protocol .................................................................................................... 32 5.3. AC-Link Output Frame (SDATA_OUT) ............................................................................................ 35 5.4. AC-Link Input Frame (SDATA_IN) .................................................................................................. 38 5.5. AC-Link Interoperability Requirements and Recommendations ...................................................... 42 5.6. Slot Assignments for Audio ............................................................................................................. 43 6. STAC9752A/9753A FUNCTIONAL BLOCKS .........................................................................46 6.1. STAC9752A/9753A Mixer Description ............................................................................................ 46 6.2. SPDIF Digital Mux ...........................................................................................................................48 6.3. PC Beep Implementation ................................................................................................................ 48 7. PROGRAMMING REGISTERS ................................................................................................50 7.1. Register Descriptions ...................................................................................................................... 51 7.2. General Purpose Input & Outputs ................................................................................................... 68 7.3. Extended CODEC Registers Page Structure Definition .................................................................. 72 7.4. STAC9752A/9753A Paging Registers ............................................................................................. 72 7.5. Vendor ID1 and ID2 (Index 7Ch and 7Eh) ...................................................................................... 84 8. LOW POWER MODES ............................................................................................................85 9. MULTIPLE CODEC SUPPORT ...............................................................................................87 9.1. Primary/Secondary CODEC Selection ............................................................................................ 87 9.2. Secondary CODEC Register Access Definitions ............................................................................. 88 10. TESTABILITY ........................................................................................................................89 10.1. ATE Test Mode ............................................................................................................................. 89 11. STAC9752A/9753A PIN DESCRIPTION ...............................................................................90 11.1. Pin Description for the 48-pin LQFP Package ............................................................................... 90 11.2. Pinout List 48-pin LQFP Package ................................................................................................ 91 11.3. Pin Description for the 32-pad QFN Package ............................................................................... 92 11.4. Pinout List 32-pad QFN Package ................................................................................................. 93 11.5. STAC9752A/9753A Digital I/O ...................................................................................................... 93 11.6. STAC9752A/9753A Analog I/O ..................................................................................................... 94 |
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