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LP3950SLX Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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LP3950SLX Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 31 page  Logic Interface Characteristics (Continued) (1.80V ≤ V DDIO ≤ V DD1,2V). Limits in standard typeface are for TJ = +25˚C. Limits in boldface type apply over the operating ambient temperature range (−40˚C ≤ T A ≤ +85˚C). Symbol Parameter Conditions Min Typ Max Units LOGIC INPUTS DME, AMODE (Internal pull down 1 M Ω) I I Logic Input Current −1.0 6.0 µA Logic Interface Characteristics, Low I/O Voltage (1.65V ≤ V DDIO < 1.80V) . I 2C compatible interface only. Symbol Parameter Conditions Min Typ Max Units LOGIC INPUTS SCL, PWM_LED, IF_SEL V IL Input Low Level 0.35 V V IH Input High Level V DDIO − 0.35 V I I Logic Input Current −1.0 1.0 µA f SCL Clock Frequency I 2C Mode 200 kHz LOGIC I/O SDA V OL Output Low Level I SDA = 3.0 mA 0.3 0.5 V LOGIC INPUTS DME, AMODE (Internal pull down 1 M Ω) V IL Input Low Level 0.35 V V IH Input High Level V DDIO − 0.35 V I I Logic Input Current −1.0 6.0 µA Logic Input NRST Characteristics (1.65V ≤ V DDIO ≤ V DD1,2V). Symbol Parameter Conditions Min Typ Max Units V IL Input Low Level 0.5 V V IH Input High Level 1.3 V I I Logic Input Current −1.0 1.0 µA t NRST Reset Pulse Width Note: Guaranteed by design 10 µs Control Interface The LP3950 supports three different interface modes: 1) SPI interface (4 wire, serial) 2) I 2C compatible interface (2 wire, serial) 3) Direct enable (2 wire, enable lines) User can define the serial interface by the IF_SEL pin. The following table shows the pin configuration for both interface modes. Note that the pin configurations will be based on the status of the IF_SEL pin. IF_SEL Interface Pin Configuration Comment HIGH SPI SCK SI SO SS (clock) (data in) (data out) (chip select) LOW I 2C Compatible SCL SDA SI SO (clock) (data in/out) (I 2 address) (NC) Use pull up resistor for SCL. Use pull up resistor for SDA. SI HIGH → address is 51’h; SI LOW → address is 50’h; Unused pin SO can be left unconnected. SPI Interface The transmission consists of 16-bit write and read cycles. One cycle consists of seven address bits, one read/write (R/W) bit and eight data bits. R/W bit high state defines a write cycle and low defines a read cycle. SO output is normally in high-impedance state and it is active only during when data is sent out during a read cycle. A pull-up or pull-down resistor may be needed for SO line if a floating logic signal can cause unintended current consumption in the circuitry. The address and data are transmitted Most Significant Byte (MSB) first. The Slave Select signal (SS) must be low during the cycle transmission. SS resets the interface when high www.national.com 8 |
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