PRELIMINARY
CY7B9945V
Document Number: 38-07336 Rev. *F
Page 5 of 11
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output[3]
Output Disable Description
The output of each output bank can be independently put into a
HOLD OFF or high impedance state. The combination of the
MODE and DIS[1:2] inputs determines the clock outputs’ state
for each bank. When the DIS[1:2] is LOW, the outputs of the
corresponding banks are enabled. When DIS[1:2] is HIGH, the
outputs for that bank are disabled to a high impedance (HI-Z) or
HOLD OFF state. Table 5 defines the disabled outputs functions.
The HOLD OFF state is a power saving feature. An output bank
is disabled to the HOLD OFF state in a maximum of six output
clock cycles from the time the disable input is HIGH. When
disabled to the HOLD OFF state, outputs are driven to a logic
LOW state on their falling edges. This makes certain that the
output clocks are stopped without a glitch. When a bank of
outputs is disabled to HI-Z state, the respective bank of outputs
go HI-Z immediately.
FBInput
REFInput
–8tU
–7tU
–6tU
–4tU
–3tU
–2tU
–1tU
0t U
+1t U
+2t U
+3t U
LL
LM
LH
(N/A)
(N/A)
(N/A)
(N/A)
MM
(N/A)
(N/A)
(N/A)
(N/A)
HL
(N/A)
LL
LM
LH
ML
MH
MM
HM
HH
(N/A)
(N/A)
(N/A)
+4tU
+6t U
+7t U
+8t U
HM
HH
HL
(N/A)
(N/A)
2F[1:0]
1F[3:2]
1F[1:0]
Table 5. DIS[1:2] Functionality
MODE
DIS[1:2]
1Q[0:3], 2Q[0:5]
HIGH/LOW
LOW
ENABLED
HIGH
HIGH
HI-Z
LOW
HIGH
HOLD-OFF
MID
X
FACTORY TEST
Notes
1. FB connected to an output selected for “Zero” skew (i.e., FBF0 = MID or XF[1:0] = MID).
2. The level set on FS is determined by the “nominal” operating frequency (fNOM) of the VCO and Phase Generator. fNOM always appears on an output when the output
is operating in the undivided mode. The REF and FB are at fNOM when the output connected to FB is undivided.
3. BK1Q denotes following the skew setting of indicated Bank1 outputs.
4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold the
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before
all data sheet limits are achieved.
5. This is for non-three level inputs.
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