IDT74SSTUBH32868A

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

COMMERCIAL TEMPERATURE GRADE

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

9

IDT74SSTUBH32868A

7105/7

Parity and Standby Function Table

Outputs

RESET

DCS0

DCS1

CLK

CLK

Σ of Inputs = H (D1 - D28)

HL

X

↑↓

Even

L

H

HL

X

↑↓

Odd

L

L

HL

X

↑↓

Even

H

L

HL

X

↑↓

Odd

H

H

HX

L

↑↓

Even

L

H

HX

L

↑↓

Odd

L

L

HX

L

↑↓

Even

H

L

HX

L

↑↓

Odd

H

H

HH

H

↑↓

XX

4

HX

X

↑↓

XX

LX or

Floating

X or

Floating

X or

Floating

X or

Floating

X or Floating

X or Floating

H

1

H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

↑ = LOW to HIGH

↓ = HIGH to LOW

2

PAR_IN arrives one clock cycle after the data to which it applies.

3

This transition assumes QERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If

QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW.

4

If DCS0, DCS1, and CSGEN are driven HIGH, the device is placed in low-power mode (LPM). If a parity

error occurs on the clock cycle before the device enters the LPM and the QERR output is driven LOW, it stays

latched LOW for the LPM plus two clock cycles or until RESET is driven LOW.