©2007 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice. NOT AN OFFER FOR SALE The information

presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale

or an offer for sale that creates a contractual power of acceptance. "QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semicondor, IDT, and Micron Tecnology, Inc."

DSC-6725/1

July 16, 2007

®

PRELIMINARY DATASHEET

IDT70P3307

IDT70P3337

Features

– Also available 9Mb Density (512K x 18)

– Commercial: 233MHz, 250MHz

– Supports concurrent transactions

– One Read and One Write request per clock cycle

– Four word burst data (Two Read and Two Write) per clock on

each port

1024K/512K x18

SYNCHRONOUS

– Four word transfers per clock cycle per port (four word bursts

on 2 ports)

receive signals from 1.4V to 1.9V

– Drives HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V

– Output impedance adjustable from 35 ohms to 70 ohms

Functional Block Diagram

(1)

OR

LEFT PORT

DATA

REGISTER

AND LOGIC

LEFT PORT

ADDRESS

REGISTER

AND LOGIC

(2)

JTAG

TCK

TRST

TMS

TDO

TDI

6725 drw01

RIGHT PORT

DATA

REGISTER

AND LOGIC

RIGHT PORT

ADDRESS

REGISTER

AND LOGIC

(2)

(1)

1024/512K x 18

MEMORY

ARRAY

WRITE DRIVER

ADDRESS DECODE

OR

NOTES:

1. Input pin to adjust the device outputs to the system data bus impedance.