Preliminary Datasheet

Commercial Temperatue Range

3

July 16, 2007

Functional Description

As a memory standard, the (Quad Data Rate) QDR-II SRAM

interface has become increasingly common in high performance

networking systems. With the QDR-II interface/configuration, memory

throughput is increased without increasing the clock rate via the use

of two unidirectional buses on each of providing 2 ports of QDR-II

makes this a Dual-QDRII Static Ram two ports to transfer data without

the need for bus turnaround.

Dual QDR-II Static RAMs are high speed synchronous mem-

ories supporting two independent double-data-rate (DDR) read and

write data ports. This scheme allows simultaneous read and write

access for the maximum device throughput - two data items are

passed with each read or write. Four data word transfers occur per

clock cycle, providing quad-data-rate (QDR) performance on each

port. Comparing this with standard SRAM common I/O single data

rate (SDR) devices, a four to one increase in data access is achieved

at equivalent clock speeds. IDT70P3307/70P3337 Dual QDR-II Static

RAM devices, are capable of sustaining full bandwidth on both the

input and output buses simultaneously. Using independent buses for

read and write data access simplifies design by eliminating the need

for bidirectional buses. And all data are in two word bursts, with

addressing capability to the burst level.

Devices with QDR-II interfaces include network processor units

(NPUs) and field programmable gate arrays (FPGAs).

IDT70P3307/70P3337 Dual QDR-II Static RAMs support uni-

directional 18-bit read and write interfaces. These data inputs and

outputs operate simultaneously, thus eliminating the need for high-

speed bus turnarounds (i.e. no dead cycles are present). Access to

each port is accomplished using a common 18-bit address bus (17

bits for IDT70P3337). Addresses for reads and writes are latched on

rising edges of the K and K input clocks, respectively. The K and K

clocks are offset by 90 degrees or half a clock cycle. Each address

location is associated with two 18-bit data words that burst sequentially

into or out of the device. Since data can be transferred into and out

of the device on every rising edge of the K and K clocks, memory

bandwidth is maximized while simplifying overall design through the

elimination of bus turnaround(s). IDT70P3307/70P3337 QDR-II Dual-

Port Static RAMs can support devices in a multi-drop configuration

(i.e. multiple devices connected to the same interface). Through this

capability, system designers can support compatible devices such as

NPUs and FPGAs on the same bus at the same time.

Using independent ports for read and write access simplifies

design by eliminating the need for bidirectional buses. All buses

associated with QDR-II Dual-Port Static RAMs are unidirectional and

can be optimized for signal integrity at very high bus speeds. The

QDR-II Dual-Port Static RAM has scalable output impedance on its

data output bus and echo clocks allowing the user to tune the bus for

low noise and high performance.

IDT70P3307/70P3337 Dual QDR-II Static RAMs have a single

DDR address bus per port with multiplexed read and write addresses.

All read addresses are received on the first half of the clock cycle and

all write addresses are received on the second half of the clock cycle.

The byte write signals are received on both halves of the clock cycle

simultaneously with the data they are controlling on the data input bus.

The Dual QDR-II Static RAM device has echo clocks, which

provide the user with a clock that is precisely timed to the data output

and tuned with matching impedance and signal quality. The user

can use the echo clock for downstream clocking of the data. For

the user, echo clocks eliminate the need to produce alternate clocks

with precise timing, positioning, and signal qualities to guarantee

data capture. Since the echo clocks are generated by the same

source that drives the data output, the relationship to the data is

NOT significantly affected by external parameters such as voltage,

temperature, and process as would be the case if the clock were

generated by an outside source. Thus the echo clocks are guar-

anteed to be synchronized with the data.

All interfaces of Dual QDR-II Static RAMs are HSTL, allow-

ing speeds beyond SRAM devices that use any form of TTL

interface. The interface can be scaled to higher voltages (up to

1.9V) to interface with 1.8V systems, if necessary. The device has

VDDQ pins and a separate Vref, allowing the user to designate the

interface operational voltage independent of the device core volt-

age of 1.8V VDD. Output impedance control pins allow the user

to adjust the drive strength to adapt to a wide range of loads and

transmission lines.

Clocking

The IDT70P3307/70P3337 has two sets of input clocks for

both the input and output, the K, K clocks and the C, C clocks. In

addition, the IDT70P3307/70P3337 has an output “echo” clock

pair, CQ and CQ.

The K and K clocks are the primary device input clocks.

The K clock is used to clock in the control signals (R, W, E[1:0],

BW

0-1), the read address, and the first word of the data burst

(D[17:0]) during a write operation. The K clock is used to clock in

word of the data burst during a write operation (D[17:0]). In the

event that the user disables the C and C clocks, the K and K clocks

will also be used to clock the data out of the output register and

generate the echo clocks. The K and K, C and C,CQ and CQ, pairs

are offset by half a clock cycle from each other.

The C and C clocks may be used to clock the data out of

the output register during read operations and to generate the echo

clocks. C and C must be presented to the memory within the timing

tolerances as shown in the AC Electrical Characteristics Table

(Page 12). The output data from the IDT70P3307/70P3337 will be

closely aligned to the C and C input, through the use of an internal

DLL. When C is presented to the IDT70P3307/70P3337 the DLL

will have already internally clocked the data to arrive at the device

output simultaneously with the arrival of the C clock. The C and

second data item of the burst will also correspond.

Single Clock Mode

The IDT70P3307/70P3337 may be operated with a single

clock pair. C and C may be disabled by tying both signals high,

forcing the outputs and echo clocks to be controlled instead by the

K and K clocks.

DLL Operation

The DLL in the output structure of the IDT70P3307/70P3337

can be used to closely align the incoming clocks C and C with the