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IDT70P3337S250RM Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT70P3337S250RM Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 20 page 18/9Mb QDR-IITM x18 IDT70P3307/70P3337 SYNCHRONOUS Dual QDR-IITM Preliminary Datasheet Commercial Temperatue Range 11 July 16, 2007 AC Electrical Characteristics (VDD = 1.8V ±100mV, VDDQ = 1.4V to 1.9V, TA(8) = 0 to 70°C) Commercial Com'l & Ind'l Symbol Parameter 250MHz 233MHz Unit Notes Min. Max. Min. Max. Clock Parameters tKHKH Average clock cycle time (K,K,C,C) 4.006.304.307.20 ns tKC var Clock Phase Jitter (K,K,C,C) __ 0.20 __ 0.20 ns 1,5 tKHKL Clock High Time (K,K,C,C)1.60 __ 1.80 __ ns 9 tKLKH Clock LOW Time (K,K,C,C)1.60 __ 1.80 __ ns 9 tKHKH Clock to clock (K →K,C→C)1.80 __ 2.00 __ ns 10 tKHKH Clock to clock (K →K,C→C) 1.80 __ 2.00 __ ns 10 tKHCH Clock to data clock (K →C,K→C) 0.00 1.80 0.00 2.00 ns tKC lock DLL lock time (K, C) 1024 __ 1024 __ cycles 2 tKC reset K static to DLL reset 30 __ 30 __ ns Output Parameters tCHQV C,C HIGH to output valid __ 0.45 __ 0.45 ns 3 tCHQX C,C HIGH to output hold -0.45 __ -0.45 __ ns 3 tCHCQV C,C HIGH to echo clock valid __ 0.45 __ 0.45 ns 3 tCHCQX C,C HIGH to echo clock hold -0.45 __ -0.45 __ ns 3 tCQHQV CQ,CQ HIGH to output valid __ 0.30 __ 0.32 ns tCQHQX CQ,CQ HIGH to output hold -0.30 __ -0.32 __ ns tCHQZ C HIGH to output High-Z __ 0.45 __ 0.45 ns 3,4,5 tCHQX1 C HIGH to output Low-Z -0.45 __ -0.45 __ ns 3,4,5 Set-Up Times tAVKH Address valid to K,K rising edge 0.35 __ 0.37 __ ns 6 tIVKH Control inputs valid to K,K rising edge 0.35 __ 0.37 __ ns 7 tDVKH Date-in valid to K, K rising edge 0.35 __ 0.37 __ ns Hold Times tKHAX K,K rising edge to address hold 0.35 __ 0.37 __ ns 6 tKHIX K,K rising edge to control inputs hold 0.35 __ 0.37 __ ns 7 tKHDX K,K rising edge to data-in hold 0.35 __ 0.37 __ ns Port-to-Port Delay tCO Clock-to-Clock Offset 4.00 — 4.30 — ns 6725 tbl15 NOTES: 1. Cycle to cycle period jitter is the variance from clock rising edge to the next expected clock rising edge, as defined per JEDEC Standard No. 65 (EIA/JESD65) page. 2. VDD slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once VDD, VDDQ and input clock are stable. 3. If C, C are tied High, K, K become the references for C, C timing parameters. 4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at 0°C and 1.9V tCHQZ, is a MAX parameter that is worst case at 70°C and 1.7V. 5. This parameter is guaranteed by device characterization, but not production tested. 6. All address inputs must meet the specified setup and hold times for all latching clock edges. 7. Control signals are R, W, BW0, BW1, E0, E1. 8. During production testing, the case temperature equals TA. 9. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60%of the cycle time (tKHKH). 10. Clock to Clock time (tKHKH) and Clock to Clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH). |
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