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MK1581-01GILFTR Datasheet(PDF) 6 Page - Integrated Device Technology |
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MK1581-01GILFTR Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 11 page MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER IDT™ / ICS™ LOW PHASE NOISE T1/E1 CLOCK GENERATOR 6 MK1581-01 REV D 073007 Recommended Power Supply Connection for Optimal Device Performance Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground, shown as CL in the External Component Schematic. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. In most cases the load capacitors will not be required. They should not be stuffed on the prototype evaluation board as the indiscriminate use of these trim capacitors will typically cause more crystal centering error than their absence. If the need for the load capacitors is later determined, the values will fall within the 1-4 pF range. The need for, and value of, these trim capacitors can only be determined at prototype evaluation. Refer to MAN05 for the centering capacitor selection procedure. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Please also refer to the Recommended PCB Layout drawing on Page 7. 1) Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No via’s should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) The loop filter components must also be placed close to the CHGP and VIN pins. CP should be closest to the device. Coupling of noise from other system signal traces should be minimized by keeping traces short and away from active signal traces. Use of vias should be avoided. 3) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 4) To minimize EMI the 33 Ω series termination resistor, if needed, should be placed close to the clock output. 5) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the MK1581-01. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. The IDT Applications Note MAN05 may also be referenced for additional suggestions on layout of the crystal section. C onnec tion to 3.3V Pow er Plane Ferrite B ead B ulk D ec oupling C apac itor (suc h as 1 F Tantalum ) VD D Pin VD D Pin VD D Pin 0.01 F D ecoupling C apacitors |
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