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ICS1893CYI-10LF Datasheet(PDF) 7 Page - Integrated Circuit Systems |
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ICS1893CYI-10LF Datasheet(HTML) 7 Page - Integrated Circuit Systems |
7 / 143 page Table of Contents ICS1893CY-10 Rev 1/07 7 ICS1893CY-10 - Release Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. Table of Contents Section Title Page 7.14 Register 19: Extended Control Register 2 ............................................................. 95 7.14.1 Node/Repeater Configuration (bit 19.15) ...............................................................96 7.14.2 Hardware/Software Priority Status (bit 19.14) ........................................................ 96 7.14.3 Remote Fault (bit 19.13) ........................................................................................ 96 7.14.4 ICS Reserved (bits 19.12:8) ................................................................................... 96 7.14.5 Auto-MDI/MDIX (bits 19. 9:8) (New) ...................................................................... 96 7.14.6 Twisted Pair Tri-State Enable, TPTRI (bit 19.7)...................................................... 97 7.14.7 ICS Reserved (bits 19.6:1) ..................................................................................... 97 7.14.8 Automatic 100Base-TX Power-Down (bit 19.0) ..................................................... 97 Chapter 8 Pin Diagram, Listings, and Descriptions ....................................................................... 98 8.1 ICS1893CY-10 Pin Diagram ..................................................................................98 8.2 ICS1893CY-10 Pin Listings .................................................................................... 99 8.3 ICS1893CY-10 Pin Descriptions ..........................................................................100 8.3.1 Transformer Interface Pins .................................................................................. 100 8.3.2 Multi-Function (Multiplexed) Pins: PHY Address and LED Pins .......................... 101 8.3.3 Configuration Pins ................................................................................................ 104 8.3.4 MAC/Repeater Interface Pins .............................................................................. 106 8.3.5 Reserved Pins ...................................................................................................... 114 8.3.6 Ground and Power Pins .......................................................................................114 Chapter 9 DC and AC Operating Conditions................................................................................. 115 9.1 Absolute Maximum Ratings ................................................................................. 115 9.2 Recommended Operating Conditions .................................................................. 115 9.3 Recommended Component Values ..................................................................... 116 9.4 DC Operating Characteristics .............................................................................. 117 9.4.1 DC Operating Characteristics for Supply Current ................................................117 9.4.2 DC Operating Characteristics for TTL Inputs and Outputs .................................. 117 9.4.3 DC Operating Characteristics for REF_IN ........................................................... 118 9.4.4 DC Operating Characteristics for Media Independent Interface .......................... 118 9.5 Timing Diagrams .................................................................................................. 119 9.5.1 Timing for Clock Reference In (REF_IN) Pin ....................................................... 119 9.5.2 Timing for Transmit Clock (TXCLK) Pins .............................................................120 9.5.3 Timing for Receive Clock (RXCLK) Pins .............................................................. 121 9.5.4 100M MII / 100M Stream Interface: Synchronous Transmit Timing ..................... 122 9.5.5 10M MII: Synchronous Transmit Timing .............................................................. 123 9.5.6 MII / 100M Stream Interface: Synchronous Receive Timing ................................ 124 9.5.7 MII Management Interface Timing ....................................................................... 125 9.5.8 10M Serial Interface: Receive Latency ................................................................ 126 9.5.9 10M Media Independent Interface: Receive Latency ........................................... 127 |
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