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C8051F338-GM Datasheet(PDF) 5 Page - Silicon Laboratories |
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C8051F338-GM Datasheet(HTML) 5 Page - Silicon Laboratories |
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5 / 234 page  Rev. 0.2 5 C8051F336/7/8/9 19.3.Programmable Internal Low-Frequency (L-F) Oscillator ................................ 120 19.3.1.Calibrating the Internal L-F Oscillator..................................................... 120 19.4.External Oscillator Drive Circuit...................................................................... 121 19.4.1.External Crystal Example....................................................................... 123 19.4.2.External RC Example............................................................................. 125 19.4.3.External Capacitor Example................................................................... 125 20. Port Input/Output.................................................................................................. 126 20.1.Port I/O Modes of Operation........................................................................... 127 20.1.1.Port Pins Configured for Analog I/O....................................................... 127 20.1.2.Port Pins Configured For Digital I/O....................................................... 128 20.1.3.Interfacing Port I/O to 5V Logic .............................................................. 128 20.2.Assigning Port I/O Pins to Analog and Digital Functions................................ 129 20.2.1.Assigning Port I/O Pins to Analog Functions ......................................... 129 20.2.2.Assigning Port I/O Pins to Digital Functions........................................... 130 20.2.3.Assigning Port I/O Pins to External Digital Event Capture Functions .... 130 20.3.Priority Crossbar Decoder .............................................................................. 131 20.4.Port I/O Initialization ....................................................................................... 133 20.5.Port Match ...................................................................................................... 136 20.6.Special Function Registers for Accessing and Configuring Port I/O .............. 138 21. SMBus ................................................................................................................... 145 21.1.Supporting Documents ................................................................................... 145 21.2.SMBus Configuration...................................................................................... 146 21.3.SMBus Operation ........................................................................................... 146 21.3.1.Transmitter Vs. Receiver........................................................................ 147 21.3.2.Arbitration............................................................................................... 147 21.3.3.Clock Low Extension.............................................................................. 148 21.3.4.SCL Low Timeout................................................................................... 148 21.3.5.SCL High (SMBus Free) Timeout .......................................................... 148 21.4.Using the SMBus............................................................................................ 148 21.4.1.SMBus Configuration Register............................................................... 149 21.4.2.SMB0CN Control Register ..................................................................... 152 21.4.2.1.Software ACK Generation ............................................................. 152 21.4.2.2.Hardware ACK Generation ............................................................ 152 21.4.3.Hardware Slave Address Recognition ................................................... 155 21.4.4.Data Register ......................................................................................... 157 21.5.SMBus Transfer Modes.................................................................................. 158 21.5.1.Write Sequence (Master) ....................................................................... 158 21.5.2.Read Sequence (Master) ....................................................................... 159 21.5.3.Write Sequence (Slave) ......................................................................... 160 21.5.4.Read Sequence (Slave) ......................................................................... 161 21.6.SMBus Status Decoding................................................................................. 161 22. UART0.................................................................................................................... 166 22.1.Enhanced Baud Rate Generation................................................................... 167 22.2.Operational Modes ......................................................................................... 168 |
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