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July 19, 2007

IDT 89HPES64H16 Data Sheet

As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure

3(a), the master and slave SMBuses are tied together and the PES64H16 acts both as a SMBus master as well as a SMBus slave on this bus. This

requires that the SMBus master or processor that has access to PES64H16 registers supports SMBus arbitration. In some systems, this SMBus

master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To

support these systems, the PES64H16 may be configured to operate in a split configuration as shown in Figure 3(b).

In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.

The PES64H16 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of

the serial EEPROM.

Figure 3 SMBus Interface Configuration Examples

Hot-Plug Interface

The PES64H16 supports PCI Express Hot-Plug on each downstream port (ports 1 through 15). To reduce the number of pins required on the

device, the PES64H16 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following

reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES64H16 generates an SMBus transaction to the I/O

expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on

the IOEXPINTN input pin (alternate function of GPIO) of the PES64H16. In response to an I/O expander interrupt, the PES64H16 generates an

SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.

General Purpose Input/Output

The PES64H16 provides 32 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose

outputs, or alternate functions. Some GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software,

SMBus slave interface, or serial configuration EEPROM.

Bit

Slave

SMBus

Address

Master

SMBus

Address

1

SSMBADDR[1]

MSMBADDR[1]

2

SSMBADDR[2]

MSMBADDR[2]

3

SSMBADDR[3]

MSMBADDR[3]

4

0

MSMBADDR[4]

5

SSMBADDR[5]

1

61

0

71

1

Table 1 Master and Slave SMBus Address Assignment

Processor

PES64H16

SSMBCLK

SSMBDAT

MSMBCLK

MSMBDAT

SMBus

Master

Other

SMBus

Devices

Serial

EEPROM

Processor

PES64H16

SSMBCLK

SSMBDAT

MSMBCLK

MSMBDAT

SMBus

Master

Other

SMBus

Devices

Serial

EEPROM

...

...

(a) Unified Configuration and Management Bus

(b) Split Configuration and Management Buses