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89HPES32H8ZAALI Datasheet(PDF) 9 Page - Integrated Device Technology

Part # 89HPES32H8ZAALI
Description  32-Lane 8-Port PCI Express System Interconnect Switch
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

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July 19, 2007
IDT 89HPES32H8 Data Sheet
Signal
Type
Name/Description
JTAG_TCK
I
JTAG Clock. This is an input test clock used to clock the shifting of data into or out of
the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system
clock with a nominal 50% duty cycle.
JTAG_TDI
I
JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG
Controller.
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary scan logic or
JTAG Controller. When no data is being shifted out, this signal is tri-stated.
JTAG_TMS
I
JTAG Mode. The value on this signal controls the test mode select of the boundary
scan logic or JTAG Controller.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary scan logic
and JTAG TAP Controller. An external pull-up on the board is recommended to meet
the JTAG specification in cases where the tester can access this signal. However, for
systems running in functional mode, one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 6 Test Pins
Signal
Type
Name/Description
VDDCORE
I
Core VDD. Power supply for core logic.
VDDIO
I
I/O VDD. LVTTL I/O buffer power supply.
VDDPE
I
PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
VDDAPE
I
PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
VSS
I
Ground.
VTTPE
PCI Express Serial Data Transmit Termination Voltage. This pin allows
the driver termination voltage to be set, enabling the system designer to
control the Common Mode Voltage and output voltage swing of the corre-
sponding PCI Serial Data Transmit differential pair.
Table 7 Power and Ground Pins


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