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ICS9FG108YGLF-T Datasheet(PDF) 4 Page - Integrated Device Technology

Part # ICS9FG108YGLF-T
Description  Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS9FG108YGLF-T Datasheet(HTML) 4 Page - Integrated Device Technology

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IDTTM/ICSTM
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
4
Pin Description (continued)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
25
DIF_STOP#
IN
Active low input to stop differential output clocks.
26
**SPREAD
IN
Asynchronous, active high input to enable spread spectrum functionality.
27
*SEL14M_25M#
IN
Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz, 0 = 25 MHz
28
**OE_3
IN
Active high input for enabling output 3.
0 = tri-state outputs, 1= enable outputs
29
DIF_3#
OUT
0.7V differential complement clock output
30
DIF_3
OUT
0.7V differential true clock output
31
VDD
PWR
Power supply, nominal 3.3V
32
DIF_2#
OUT
0.7V differential complement clock output
33
DIF_2
OUT
0.7V differential true clock output
34
*OE_2
IN
Active high input for enabling output 2.
0 = tri-state outputs, 1= enable outputs
35
GND
PWR
Ground pin.
36
VDD
PWR
Power supply, nominal 3.3V
37
*OE_1
IN
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
38
DIF_1#
OUT
0.7V differential complement clock output
39
DIF_1
OUT
0.7V differential true clock output
40
VDD
PWR
Power supply, nominal 3.3V
41
DIF_0#
OUT
0.7V differential complement clock output
42
DIF_0
OUT
0.7V differential true clock output
43
**OE_0
IN
Active high input for enabling output 0.
0 = tri-state outputs, 1= enable outputs
44
**FS1
I/O
Frequency select latch input pin / 3.3V 66.66MHz clock output.
45
**FS0
IN
3.3V Frequency select latched input pin.
46
IREF
OUT
This pin establishes the reference current for the differential current-mode output
pairs. This pin requires a fixed precision resistor tied to ground in order to establish
the appropriate current. 475 ohms is the standard value.
47
GNDA
PWR
Ground pin for the PLL core.
48
VDDA
PWR
3.3V power for the PLL core.
Note:
Pin names followed by '**' have 120 Kohm pull DOWN resistors
Pin names followed by '*' have 120 Kohm pull UP resistors


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