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ICS9FG108 Datasheet(PDF) 3 Page - Integrated Device Technology

Part # ICS9FG108
Description  Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS9FG108 Datasheet(HTML) 3 Page - Integrated Device Technology

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IDTTM/ICSTM
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
3
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
XIN/CLKIN
IN
Crystal input or Reference Clock input
2
X2
OUT
Crystal output, Nominally 14.318MHz
3
VDD
PWR
Power supply, nominal 3.3V
4
GND
PWR
Ground pin.
5
REFOUT
OUT
Reference Clock output
6
**FS2
IN
Frequency select pin.
7
**OE_7
IN
Active high input for enabling output 7.
0 = tri-state outputs, 1= enable outputs
8
DIF_7
OUT
0.7V differential true clock output
9
DIF_7#
OUT
0.7V differential complement clock output
10
VDD
PWR
Power supply, nominal 3.3V
11
DIF_6
OUT
0.7V differential true clock output
12
DIF_6#
OUT
0.7V differential complement clock output
13
*OE_6
IN
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
14
VDD
PWR
Power supply, nominal 3.3V
15
GND
PWR
Ground pin.
16
*OE_5
IN
Active high input for enabling output 5.
0 = tri-state outputs, 1= enable outputs
17
DIF_5
OUT
0.7V differential true clock output
18
DIF_5#
OUT
0.7V differential complement clock output
19
VDD
PWR
Power supply, nominal 3.3V
20
DIF_4
OUT
0.7V differential true clock output
21
DIF_4#
OUT
0.7V differential complement clock output
22
**OE_4
IN
Active high input for enabling output 4.
0 = tri-state outputs, 1= enable outputs
23
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
24
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
Note:
Pin names followed by '**' have 120 Kohm pull DOWN resistors
Pin names followed by '*' have 120 Kohm pull UP resistors


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