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M2004-02-672.1600 Datasheet(PDF) 2 Page - Integrated Circuit Systems |
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M2004-02-672.1600 Datasheet(HTML) 2 Page - Integrated Circuit Systems |
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2 / 10 page  Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com M2004-02 Preliminary Specifications 2 Micro Networks An Integrated Circuit Systems Company nF OUT F OUT Parallel Programming Interface M5:M0 Mux REF_CLK DIF_REF 0 nDIF_REF 0 MR OP_OUT nOP_OUT OP_IN nOP_IN +M Vc nVc VCSO REF_SEL N1 Phase Detector & Active Loop Filter Output Divider Functional Description: The internal PLL will adjust the VCSO output frequency to be M (feedback divider) times the selected input reference clock frequency. Note that the product of M x the input reference frequency must be such that it falls within the “lock” range of the VCSO. The N output divider can be programmed to divide the VCSO output frequency by 1, 2, 4, or 8 and provide a 50% output duty cycle. The multiplying factor is programmed via a 6-bit parallel bus. The relationship between the VCSO frequency, the M divider, and the Differential Input reference clock is defined as follows: F VCSO = F REF_CLK x M When the N output divider is included, the complete relationship for the output frequency is defined as: FOUT = F VCSO = F REF_CLK x M N N The N1 input can be hard wired to set the N divider to a specific state that will automatically occur during power-up. FUNCTIONAL BLOCK DIAGRAM |
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