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UMA1021M Datasheet(PDF) 10 Page - NXP Semiconductors |
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UMA1021M Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 16 page 1999 Jun 17 10 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021M SERIAL BUS TIMING CHARACTERISTICS VDD =VCC =3V; Tamb =25 °C; unless otherwise specified. Note 1. The minimum pulse width (tW(min)) can be smaller than 4 µs provided all the following conditions are fulfilled: a) Main divider input frequency . b) Reference divider input frequency . SYMBOL PARAMETER MIN. TYP. MAX. UNIT Serial programming clock; CLK tr input rise time − 10 40 ns tf input fall time − 10 40 ns Tcy clock period 100 −− ns Enable programming; E tSTART delay to rising clock edge 40 −− ns tEND delay from last falling clock edge −20 −− ns tW(min) minimum inactive pulse width 4000(1) −− ns tSU;E enable set-up time to next clock edge 20 −− ns Register serial input data; DATA tSU;DAT input data to clock set-up time 20 −− ns tHD;DAT input data to clock hold time 20 −− ns f RF 447 t Wmin () ------------------- > f xtal 3 t Wmin () ------------------- > Fig.3 Serial bus timing diagram. handbook, full pagewidth MGD565 MSB LSB ADDRESS tSTART tSU;DAT tHD;DAT Tcy tr tf tW(min) tEND tSU;E CLK DATA E |
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