6.42

IDT70T3509M

High-Speed 2.5V

1024K x 36 Dual-Port Synchronous Static RAM

Commercial Temperature Range

10

AC Electrical Characteristics Over the Operating Temperature Range

NOTES:

apply when

2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (

OE), FT/PIPE and OPT. FT/PIPE and OPT should be

treated as DC signals, i.e. steady state during operation.

4. Guaranteed by design (not production tested).

70T3509MS133

Com'l

& Ind

Symbol

Parameter

Min.

Max.

Unit

Clock Cycle Time (Flow-Through)

(1)

25

____

ns

7.5

____

ns

Clock High Time (Flow-Through)

(1)

10

____

ns

10

____

ns

Clock High Time (Pipelined)

(2)

3

____

ns

3

____

ns

Address Setup Time

1.8

____

ns

Address Hold Time

0.5

____

ns

Chip Enable Setup Time

1.8

____

ns

Chip Enable Hold Time

0.5

____

ns

Byte Enable Setup Time

1.8

____

ns

Byte Enable Hold Time

0.5

____

ns

R/W Setup Time

1.8

____

ns

R/W Hold Time

0.5

____

ns

Input Data Setup Time

1.8

____

ns

Input Data Hold Time

0.5

____

ns

ADS Setup Time

1.8

____

ns

ADS Hold Time

0.5

____

ns

CNTEN Setup Time

1.8

____

ns

CNTEN Hold Time

0.5

____

ns

REPEAT Setup Time

1.8

____

ns

REPEAT Hold Time

0.5

____

ns

Output Enable to Data Valid

____

4.6

ns

(4)

Output Enable to Output Low-Z

1

____

ns

Output Enable to Output High-Z

1

4.2

ns

Clock to Data Valid (Flow-Through)

(1)

____

15

ns

____

4.2

ns

Data Output Hold After Clock High

1

____

ns

Clock High to Output High-Z

1

4.2

ns

Clock High to Output Low-Z

1

____

ns

Interrupt Flag Set Time

____

7ns

Interrupt Flag Reset Time

____

7ns

Collision Flag Set Time

____

4.2

ns

Collision Flag Reset Time

____

4.2

ns

Sleep Mode Set Cycles

2

____

cycles

Sleep Mode Recovery Cycles

3

____

cycles

Port-to-Port Delay

Clock-to-Clock Offset

6

____

ns

5682 tbl 11