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September 7, 2007

IDT 89HPES8T5A Data Sheet

System Clock Parameters

Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.

AC Timing Characteristics

Parameter

Description

Min

Typical

Max

Unit

PEREFCLK

Input reference clock frequency range

100

MHz

Duty cycle of input clock

40

50

60

%

Rise/Fall time of input clocks

0.2*RCUI

0.6

1.6

V

Input clock jitter (cycle-to-cycle)

125

ps

Table 9 Input Clock Requirements

Parameter

Description

Min

Typical

Max

Units

PCIe Transmit

80

ps

UI

Unit Interval

399.88

400

400.12

ps

Transmitter Total Jitter (peak-to-peak)

UI

UI

MAX-JITTER

Maximum time between the jitter median and maximum

deviation from the median

0.15

UI

Transmitter data latency (for n=10)

9

11

bits

Transmitter data latency (for n=20)

9

11

bits

Transmitter data skew between any 2 lanes

500

1300

ps

IDLE

Maximum time to transition to a valid electrical idle after

sending an Electrical Idle ordered set

46

ns

Time to exit Electrical Idle (L0s) state into L0

12

16

ns

Time from asserting Beacon TxEn to beacon being trans-

mitted on the lane

30

80

ns

Pulse width of RxDetectEn input

9.8

10

10.2

ns

RxDetectEn falling edge to RxDetect delay

1

2

ns

PCIe Receive

Recover data latency for n=10

28

29

bits

Recover data latency for n=20

49

60

bits

Table 10 PCIe AC Timing Characteristics (Part 1 of 2)