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89HPES3T3ZABC Datasheet(PDF) 7 Page - Integrated Device Technology |
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89HPES3T3ZABC Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 23 page  7 of 23 September 7, 2007 IDT 89HPES3T3 Data Sheet Logic Diagram — PES3T3 Figure 3 PES3T3 Logic Diagram Reference Clock PEREFCLKP PEREFCLKN JTAG_TCK GPIO[9,7,2:0] 5 General Purpose I/O VDDCORE VDDI/O VDDPE VDDAPE Power/Ground CCLKUS RSTHALT System Pins JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG Pins VSS SWMODE[2:0] 3 CCLKDS PERSTN VTTPE PE0RP[0] PE0RN[0] PCI Express Switch SerDes Input PE0TP[0] PE0TN[0] PCI Express Switch SerDes Output Port 0 Port 0 PE2RP[0] PE2RN[0] PCI Express Switch SerDes Input PE2TP[0] PE2TN[0] PCI Express Switch SerDes Output Port 2 Port 2 PE3RP[0] PE3RN[0] PCI Express Switch SerDes Input PE3TP[0] PE3TN[0] PCI Express Switch SerDes Output Port 3 Port 3 PES3T3 MSMBCLK MSMBDAT Master SMBus Interface WAKEN APWRDISN |
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