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September 7, 2007

IDT 89HPES3T3 Data Sheet

Signal

Type

Name/Description

GPIO[0]

I/O

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P2RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 2

GPIO[1]

I/O

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[2]

I/O

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN0

Alternate function pin type: Input

Alternate function: I/O Expander interrupt 0 input

GPIO[7]

I/O

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: GPEN

Alternate function pin type: Output

Alternate function: General Purpose Event (GPE) output

GPIO[9]

I/O

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P3RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 3

Table 3 General Purpose I/O Pins

Signal

Type

Name/Description

APWRDISN

I

Auxiliary Power Disable Input. When this pin is active, it disables the

device from using auxiliary power supply.

CCLKDS

I

Common Clock Downstream. The assertion of this pin indicates that all

downstream ports are using the same clock source as that provided to

downstream devices.This bit is used as the initial value of the Slot Clock

Configuration bit in all of the Link Status Registers for downstream ports.

The value may be override by modifying the SCLK bit in the downstream

port’s PCIELSTS register.

CCLKUS

I

Common Clock Upstream. The assertion of this pin indicates that the

upstream port is using the same clock source as the upstream device. This

bit is used as the initial value of the Slot Clock Configuration bit in the Link

Status Register for the upstream port. The value may be overridden by

modifying the SCLK bit in the PA_PCIELSTS register.

PERSTN

I

Fundamental Reset. Assertion of this signal resets all logic inside the

PES3T3 and initiates a PCI Express fundamental reset.

Table 4 System Pins (Part 1 of 2)