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ICS557G-06 Datasheet(PDF) 2 Page - Integrated Device Technology |
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ICS557G-06 Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 11 page ICS557-06 1 TO 4 HCSL CLOCK BUFFER PCIE FAN OUT BUFFER IDT™ / ICS™ 1 TO 4 HCSL CLOCK BUFFER 2 ICS557-06 REV F 090407 Pin Assignment Select Table Pin Descriptions 13 4 12 5 11 IN2 8 9 10 GND OE CLKC CLKD GND CLKD 17 16 IREF 3 IN1 IN1 CLKB 18 CLKB 1 SEL VDDIN CLKA 20 CLKA 19 14 2 7 IN2 PD VDD CLKC 15 6 20-pin (173 mil) TSSOP SEL Input Pair selected 0IN2/ IN2 1IN1/ IN1 Pin Pin Name Pin Type Pin Description 1 SEL Input SEL=1 selects IN1/IN1. SEL =0 selects IN2/ IN2. Internal pull-up resistor. 2 VDDIN Power Connect to +3.3 V. Supply voltage for Input clocks. 3 IN1 Input HCSL/LVDS true input signal 1. 4 IN1 Input HCSL/LVDS complimentary input signal 1. 5 PD Input Powers down the chip and tri-states outputs when low. Internal pull-up 6 IN2 Input HCSL/LVDS true input signal 2. 7 IN2 Input HCSL/LVDS complimentary input signal 2. 8 OE Input Provides fast output on, tri-states output (High = enable outputs; Low = disable). Internal pull-up resistor outputs. 9 GND Power Connect to ground. 10 Rr(IREF) Output Precision resistor attached to this pin is connected to the internal current 11 CLKD Output Differential Complimentary output clock D. 12 CLKD Output Differential True output clock D. 13 CLKC Output Differential Complimentary output clock C. 14 CLKC Output Differential True output clock C. 15 VDDOUT Power Connect to +3.3 V. Supply Voltage for Output Clocks. 16 GND Power Connect to ground. 17 CLKB Output Differential Complimentary output clock B. 18 CLKB Output Differential True output clock B. 19 CLKA Output Differential Complimentary output clock A. 20 CLKA Output Differential True output clock A. |
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