PRELIMINARY

DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER

W/INTERNAL TERMINATION

ICS889872

IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION

1

ICS889872AK REV. A AUGUST 22, 2007

General Description

The ICS889872 is a high speed Differential-to-

LVDS Buffer/Divider w/Internal Termination and is a

member of the HiPerClockS™family of high

performance clock solutions from IDT. The

ICS889872 has a selectable ÷2, ÷4, ÷8, ÷16 output

dividers. The clock input has internal termination resistors,

allowing it to interface with several differential signal types while

minimizing the number of required external components. The

device is packaged in a small, 3mm x 3mm VFQFN package,

making it ideal for use on space-constrained boards.

Features

÷8, ÷16: >1.6GHz

LVPECL, LVDS, CML

packages

HiPerClockS™

ICS

ICS889872

16-Lead VFQFN

3mm x 3mm x 0.95mm package body

K Package

Top View

The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.

Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

Block Diagram

Pin Assignment

Decoder

÷2, ÷4,

÷8, ÷16

50

Ω

50

Ω

Enable

FF

Enable

MUX

QA

nQA

QB0

nQB0

QB1

nQB1

nRESET/

nDISABLE

IN

V

T

V

REF_AC

S1

S0

nIN

5

6

7

8

16 15 14 13

1

2

3

4

12

11

10

9

QB0

nQB0

QB1

nQB1

IN

nIN