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WM8804GEDSR Datasheet(PDF) 10 Page - Wolfson Microelectronics plc |
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WM8804GEDSR Datasheet(HTML) 10 Page - Wolfson Microelectronics plc |
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10 / 66 page  WM8804 Production Data w PD Rev 4.1 September 2007 10 CONTROL INTERFACE – 2-WIRE MODE SDIN SCLK t STHO t SCY t DSU t STSU t STHO t STOP t DH Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK cycle time tSCY 2500 ns SCLK duty cycle 40/60 60/40 % SCLK frequency 400 kHz Hold Time (Start Condition) tSTHO 600 ns Setup Time (Start Condition) tSTSU 600 ns Data Setup Time tDSU 100 ns SDIN, SCLK Rise Time 300 ns SDIN, SCLK Fall Time 300 ns Setup Time (Stop Condition) tSTOP 600 ns Data Hold Time tDH 900 ns SCLK glitch suppression tps 2 8 ns Table 5 Control Interface Timing – 2-Wire Serial Control Mode |
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