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SY89229U Datasheet(PDF) 6 Page - Micrel Semiconductor

Part # SY89229U
Description  1GHz Precision, LVPECL 첨3, 첨5 Clock Divider with Fail-Safe Input and Internal Termination
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

SY89229U Datasheet(HTML) 6 Page - Micrel Semiconductor

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Micrel, Inc.
SY89228U
August 2007
M9999-080707-A
hbwhelp@micrel.com or (408) 955-1690
6
AC Electrical Characteristics
(8)
VCC = 2.5V ±5% or 3.3V ±10%; RL = 50Ω to VCC-2V; TA = –40°C to + 85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Input Operating
Frequency
VOUT ≥ 200mV
1.0
1.5
GHz
tw
Minimum Pulse Width
IN, /IN
400
ps
Differential Propagation Delay
In-to-Q
100mV < VIN ≤ 200mV, Note 9
900
1150
1500
ps
In-to-Q
200mV < VIN ≤ 800mV, Note 9
800
1050
1400
ps
tpd
/MR(H-L)-to-Q
350
570
850
ps
tRR
Reset Recovery Time
/MR(L-H)-to-IN
300
ps
tS EN
Set-up Time
EN-to-IN Note 10
300
ps
tH EN
Hold Time
IN-to-EN Note 10
800
ps
tskew
Part-to-Part Skew
Note 10
450
ps
Clock
Random Jitter
Note 11
1
psRMS
Cycle-to-Cycle Jitter
Note 12
1
psRMS
tJITTER
Total Jitter
Note 13
10
psPP
tr, tf
Output Rise/Fall Time (20% to
80%)
At full output swing.
100
270
ps
Output Duty Cycle(÷ 3)
Duty Cycle(input): 50%; f ≤1GHz;
Note 14
46
54
%
Output Duty Cycle(÷ 5)
Duty Cycle(input): 50%; f ≤1GHz;
Note 14
47
53
%
Notes:
8. High-frequency AC-parameters are guaranteed by design and characterization.
9. The propagation delay is function of the rise and fall times at IN. Input tr / tf ≤ 300ps (20% to 80%). See “Typical Operating Characteristics”
for details.
10. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous
applications, set-up and hold do not apply.
11. Random Jitter is measured with a K28.7 character pattern, measured at <fMAX.
12. Cycle-to-Cycle Jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the
output signal.
13. Total Jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 10
12 output edges will deviate by more
than the specified peak-to-peak jitter value.
14. For Input Duty Cycle different from 50%, see “Output Duty Cycle Equation” in “Functional Description” subsection.


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