CY2305C
CY2309C
Document Number: 38-07672 Rev. *H
Page 3 of 12
CY2309C
Figure 2. Pin Diagram - 16 Pin SOIC/TSSOP
Table 2. Pin Definition - 16 Pin SOIC/TSSOP
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal
feedback to the PLL, its relative loading can adjust the input or output delay.
For applications requiring zero input or output delay, all outputs including CLKOUT are equally loaded. Even if CLKOUT is not used,
it must have a capacitive load equal to that on other outputs for obtaining zero input or output delay.
For zero output or output skew, all outputs are loaded equally. For further information refer to the application note entitled “CY2305
and CY2309 as PCI and SDRAM Buffers”.
Pin
Signal
Description
1REF[1]
Input reference frequency
2
CLKA1[2]
Buffered clock output, Bank A
3
CLKA2[2]
Buffered clock output, Bank A
4VDD
3.3V supply
5
GND
Ground
6
CLKB1[2]
Buffered clock output, Bank B
7
CLKB2[2]
Buffered clock output, Bank B
8S2[3]
Select input, bit 2
9S1[3]
Select input, bit 1
10
CLKB3[2]
Buffered clock output, Bank B
11
CLKB4[2]
Buffered clock output, Bank B
12
GND
Ground
13
VDD
3.3V supply
14
CLKA3[2]
Buffered clock output, Bank A
15
CLKA4[2]
Buffered clock output, Bank A
16
CLKOUT[2]
Buffered output, internal feedback on this pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
Top View
CY2309C
Notes
3. Weak pull ups on these inputs.
4. This output is driven and has an internal feedback for the PLL. The load on this output is adjusted to change the skew between the reference and output.
Table 3. Select Input Decoding for CY2309C
S2
S1
CLOCK A1–A4
CLOCK B1–B4
CLKOUT[4]
Output Source
PLL Shutdown
0
0
Three state
Three state
Driven
PLL
N
0
1
Driven
Three state
Driven
PLL
N
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
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