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CG5982AF Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CG5982AF
Description  2K x 8 Automotive Dual-port Static RAM
Download  12 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CG5982AF Datasheet(HTML) 4 Page - Cypress Semiconductor

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CG5982AF
Document #: 38-06067 Rev. *C
Page 4 of 12
tHZOE
OE HIGH to High-Z[8, 11, 12]
25
ns
tHZCE
CE HIGH to High-Z[8, 11, 12]
25
ns
tPU
CE LOW to Power-Up[8]
0
ns
tPD
CE HIGH to Power-Down[8]
35
ns
Write Cycle[13]
tWC
Write Cycle Time
55
ns
tSCE
CE LOW to Write End
40
ns
tAW
Address Set-up to Write End
40
ns
tHA
Address Hold from Write End
2
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
R/W Pulse Width
30
ns
tSD
Data Set-up to Write End
20
ns
tHD
Data Hold from Write End
0
ns
tHZWE
R/W LOW to High-Z [8]
25
ns
tLZWE
R/W HIGH to Low-Z [8]
0
ns
Busy/Interrupt Timing
tBLA
BUSY LOW from Address Match
30
ns
tBHA
BUSY HIGH from Address Mismatch[14]
30
ns
tBLC
BUSY LOW from CE LOW
30
ns
tBHC
BUSY HIGH from CE HIGH[14]
30
ns
tPS
Port Set-up for Priority
5
ns
tWB
R/W LOW after BUSY LOW
0
ns
tWH
R/W HIGH after BUSY HIGH
35
ns
tBDD
BUSY HIGH to Valid Data
45
ns
tDDD
Write Data Valid to Read Data Valid
Note 15
ns
tWDD
Write Pulse to Data Delay
Note 15
ns
Interrupt Timing[15]
tWINS
R/W to INTERRUPT Set Time
45
ns
tEINS
CE to INTERRUPT Set Time
45
ns
tINS
Address to INTERRUPT Set Time
45
ns
tOINR
OE to INTERRUPT Reset Time[14]
45
ns
tEINR
CE to INTERRUPT Reset Time[14]
45
ns
tINR
Address to INTERRUPT Reset Time[14]
45
ns
Notes:
12. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE, and tHZWE are tested with CL = 5 pF, as in (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
13. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
14. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
15. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
Switching Characteristics Over the Operating Range[4, 9] (continued)
Parameter
Description
CG5982AF
Unit
Min.
Max.
[+] Feedback
[+] Feedback


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