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CDB4341 Datasheet(PDF) 11 Page - Cirrus Logic

Part # CDB4341
Description  24-Bit, 96 kHz Stereo DAC with Volume Control
Download  34 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CDB4341 Datasheet(HTML) 11 Page - Cirrus Logic

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CS4341
DS298F5
11
SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK
Notes: 6. The Duty Cycle must be 50%
+/− 1/2 MCLK Period.
7. See section 4.2.1 for derived internal frequencies.
Parameters
Symbol
Min
Typ
Max
Units
MCLK Frequency
1.024
-
51.2
MHz
MCLK Duty Cycle
45
-
55
%
Input Sample Rate
Single-Speed Mode
Double-Speed Mode
Fs
Fs
4
50
-
-
50
100
kHz
kHz
LRCK Duty Cycle
(Note 6)
%
SCLK Period
(Note 7)
tsclkw
--
s
SCLK rising to LRCK edge
tsclkr
--
s
SDATA valid to SCLK rising setup time
tsdlrs
--
ns
SCLK rising to SDATA hold time
MCLK / LRCK = 512, 256 or 128
tsdh
--
ns
SCLK rising to SDATA hold time
MCLK / LRCK = 384 or 192
tsdh
--
ns
1
SCLK
----------------
t
sclkw
2
--------------
1
512
()Fs
----------------------10
+
1
512
()Fs
----------------------15
+
1
384
()Fs
----------------------15
+
SDATA
*INTERNAL SCLK
LRCK
sclkw
t
sdlrs
t
sdh
t
sclkr
t
Figure 12. Internal Serial Mode Input Timing
*The SCLK pulses shown are internal to the CS4341.
SDATA
LRCK
MCLK
*INTERNAL SCLK
1
N
2
N
Figure 13. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4341. N equals MCLK divided by SCLK


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