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UDA1335H Datasheet(PDF) 9 Page - NXP Semiconductors |
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UDA1335H Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 44 page 1998 Aug 28 9 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H FUNCTIONAL DESCRIPTION The Universal Serial Bus (USB) Data and power is transferred via the USB over a 4-wire cable. The signalling occurs over two wires and point-to-point segments. The signals on each segment are differentially driven into a cable of 90 Ω intrinsic impedance. The differential receiver features input sensitivity of at least 200 mV and sufficient common mode rejection. The analog front-end The analog front-end is an on-chip generic USB transceiver. It is designed to allow voltage levels up to VDD from standard or programmable logic to interface with the physical layer of the USB. It is capable of receiving and transmitting serial data at full speed (12 Mbits/s). The USB processor The USB processor forms the interface between the analog front-end, the ADIF, the ADAC and the microcontroller. The USB processor consists of: • The Philips Serial Interface Engine (PSIE) • The Memory Management Unit (MMU) • The Audio Sample Redistribution (ASR) module. The Philips Serial Interface Engine and Memory Management Unit (PSIE/MMU) The PSIE/MMU translates the electrical USB signals into bytes and signals. Depending upon the USB device address and the USB endpoint address, the USB data is directed to the correct endpoint buffer on the PSIE/MMU interface. The data transfer could be of bulk, isochronous, control or interrupt type. The USB device address is configured during the enumeration process. The UDA1335H has four endpoints. These are: • Control endpoint 0 • Status interrupt endpoint • Isochronous data sink endpoint • Isochronous data source endpoint. The amount of bytes/packet on the control endpoint is limited by the PSIE/MMU hardware to 8 bytes/packet. The PSIE is the digital front-end of the USB processor. This module recovers the 12 MHz USB clock, detects the USB sync word and handles all low-level USB protocols and error checking. The MMU is the digital back-end of the USB processor. It handles the temporary data storage of all USB packets that are received or sent over the bus. Three types of packets are defined on the USB. These are: • Token packets • Data packets • Handshake packets. The token packet contains information about the destination of the data packet. The audio data is transferred via an isochronous data sink endpoint or source endpoint and, consequently, no handshaking mechanism is used. The MMU also generates a 1 kHz clock that is locked to the USB Start Of Frame (SOF) token. The Audio Sample Redistribution (ASR) The ASR reads the audio samples from the MMU and distributes these samples equidistant over a 1 ms frame period. The distributed audio samples are translated by the digital I/O module to standard I2S-bus format or Japanese digital I/O format. The ASR generates the bit clock and the word select signal of the digital I/O. The digital I/O formats the received audio samples to one of the four specified serial digital audio formats (I2S-bus, 16, 18 or 20 bits LSB-justified). The microcontroller The microcontroller receives the control information selected from the USB by the USB processor. It handles the high-level USB protocols and the user interfaces. The major task of the software process, that is mapped upon the microcontroller, is to control the different modules of the UDA1335H in such a way that it behaves as a USB device. Therefore the microcontroller: • Interprets the USB requests and maps them upon the UDA1335H application • Controls the internal operation of the UDA1335H, the digital I/O pins and the GP I/O pins • Communicates with the external world (external controller, EEPROM) using the I2C-bus facility and the GP I/O pins. The microcontroller does not handle the audio stream. The UDA1335H will be delivered with USB compliant firmware. The firmware must be located in an external (E)PROM. |
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