Vortex86SX
32-Bit x86 Embedded SoC
Vortex86SX Brief Datasheet
Version 1.001
9
D11
MA[9]/Strap[9]
I/O
Memory Address MA[9]. Normally, these pins are used as the row and
column address for SDRAM/DDR.
Strap[9]. Pulled low: 33 PINS is for IDE2.
Pulled high: 33 PINS is for COM3/4 and Parallel Port. Default internal
pull-high.
A12
MA[10]/Strap[10]
I/O
Memory Address MA[10]. Normally, these pins are used as the row and
column address for SDRAM/DDR.
Strap[4]/[10]. SDRAM/DDR clock, Default pull low.
Strap[10]
Strap[4]
Memory clock
0
0
100MHz
0
1
133MHz (Internal default)
1
0
166MHz
1
1
200MHz
E11
MA[11]/Strap[11]
I/O
Memory Address MA[11]. Normally, these pins are used as the row and
column address for SDRAM/DDR.
Strap[11]. Pulled low is Internal RTC. Default internal pull-low.
Pulled high is External RTC
F11,F10
MA[13:12]/
Strap[13:12]
I/O
Memory Address MA[13:12]. Normally, these pins are used as the row and
column address for SDRAM/DDR.
Strap[13:12]. 00 : flash-8bits
01 : flash-16bits
11 : Internal SPI. Default internal pull-high.
USB 0, 1, 2, 3 (10 PINs)
PIN No.
Symbol
Type
Description
N26
N25
USB0_DP
USB0_DM
I/O
Universal Serial Bus Controller 0 Port 0. These are the serial data pair
for USB Port 0. 15kΩ pull down resistors are connected to DP and DM
internally.
M26
M25
USB1_DP
USB1_DM
I/O
Universal Serial Bus Controller 0 Port 1. These are the serial data pair
for USB Port 1. 15kΩ pull down resistors are connected to DP and DM
internally.
T26
T25
USB2_DP
USB2_DM
I/O
Universal Serial Bus Controller 1 Port 0. These are the serial data pair
for USB Port 2. 15kΩ pull down resistors are connected to DP and DM
internally.
R26
R25
USB3_DP
USB3_DM
I/O
Universal Serial Bus Controller 1 Port 1. These are the serial data pair
for USB Port 3. 15kΩ pull down resistors are connected to DP and DM
internally.
P26
REXT[0]:
I
Universal Serial Bus Controller 0 External Reference Resistance. 510Ω
±
10%
U26
REXT[1]:
I
Universal Serial Bus Controller 1 External Reference Resistance. 510Ω
±
10%
PCI Bus Interface (56 PINs)
PIN No.
Symbol
Type
Description
B19, B18, C18
PREQ_[2:0]
I
PCI Bus Request. These signals are the PCI bus request signals used as
inputs by the internal PCI arbiter.
D19, D18 ,C19
PGNT_[2:0]
O
PCI Bus Grant. These signals are the PCI bus grant output signals generated
by the internal PCI arbiter.
D26
PCIRST_
O
PCI Reset. This pin is used to reset PCI devices. When it is asserted low, all
the PCI devices will be reset.
A19
A18
A20
PCICLK_0
PCICLK_1
PCICLK_2
O
PCI Clock Output. This clock is used by all of the Vortex86SX logic that is in
the PCI clock domain.
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