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P1754-30QGMB Datasheet(PDF) 4 Page - Pyramid Semiconductor Corporation

Part # P1754-30QGMB
Description  SINGLE CHIP, 40MHz CMOS PROCESSOR INTERFACE CIRCUIT (PIC)
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Manufacturer  PYRAMID [Pyramid Semiconductor Corporation]
Direct Link  http://www.pyramidsemiconductor.com
Logo PYRAMID - Pyramid Semiconductor Corporation

P1754-30QGMB Datasheet(HTML) 4 Page - Pyramid Semiconductor Corporation

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PACE1754
Page 4 of 20
Document # MICRO-5 REV C
AC ELECTRICAL CHARACTERISTICS
1, 2
(VCC = 5V ± 10% Over Recommended Operating Conditions)
20 MHz
30MHz
40 MHz
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Unit
tEX RDY (RDYD)V
Time from External Ready to
16
14
12
ns
Ready Data Valid
tC (RDYD)V
Time from Clock Read to
28
22
16
ns
Ready Data Valid
tSTRBAH (A)V
Time from Strobe Address HIGH to
29
21
19
ns
Address Bus Valid
tIBAV (A)V
Time from Information Bus Address to
31
22
20
ns
Address Bus Valid
tFC (R)L
Time from Falling Clock to
24
18
12
ns
Read LOW
t
STRBDH (R)H
Time from Strobe Data HIGH to
24
18
12
ns
Read HIGH
t
STRBDL (W)L
Time from Strobe Data LOW to
26
20
15
ns
Write LOW
t
STRBDH (W)H
Time from Strobe Data HIGH to
26
20
15
ns
Write HIGH
tIBDIN (ME PA ER)L
Time from Information Bus Data into
22
17
12
ns
Memory Parity Error LOW
tIBAIN (EX AD ER)
Time from Information Bus Address into
30
25
20
ns
External Address Error
t
STRBDL
Time from Strobe Data LOW to
26
20
15
ns
(STRT ROM)V
Start-up ROM Valid
tFC (IB OUT)V
Time from Falling Clock to
30
25
25
ns
Information Bus Valid
tC (TIMER CLK)
Time from Rising Edge of Clock to
30
25
20
ns
Timer Clock
tIB INV (IB16)
Time from Information Bus Data to
25
20
18
ns
Parity Valid
tEXT AD (CLKB3)
Extended Address
10
10
10
ns
Setup Time
t
EX RDY1 (RDYD)V
Time from External Ready Data to
28
24
21
ns
Ready Data Valid
tFC (
SCR EN)
Time from Falling Clock to SCR Enable;
30
24
24
ns
Case Types T and X only
t
STRBDH (SCR EN)
Time from STRBD HIGH to SCR Enable;
30
24
24
ns
Case Types T and X only
Notes:
1. 4.5V
≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
2. All measurements of delay times on active signals are related to the 1.5V levels.


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