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SN74LVTH373DBLE Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LVTH373DBLE Datasheet(HTML) 1 Page - Texas Instruments |
1 / 16 page SN54LVTH373, SN74LVTH373 3.3V ABT OCTAL TRANSPARENT DTYPE LATCHES WITH 3STATE OUTPUTS SCBS689H − MAY 1997 − REVISED OCTOBER 2003 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) D Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D Support Unregulated Battery Operation Down to 2.7 V D Ioff and Power-Up 3-State Support Hot Insertion D Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors D Latch-Up Performance Exceeds 500 mA Per JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) description/ordering information These octal latches are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC − DW Tube SN74LVTH373DW LVTH373 SOIC − DW Tape and reel SN74LVTH373DWR LVTH373 −40 °C to 85°C SOP − NS Tape and reel SN74LVTH373NSR LVTH373 −40 °C to 85°C SSOP − DB Tape and reel SN74LVTH373DBR LXH373 TSSOP − PW Tube SN74LVTH373PW LXH373 TSSOP − PW Tape and reel SN74LVTH373PWR LXH373 CDIP − J Tube SNJ54LVTH373J SNJ54LVTH373J −55 °C to 125°C CFP − W Tube SNJ54LVTH373W SNJ54LVTH373W −55 C to 125 C LCCC - FK Tube SNJ54LVTH373FK SNJ54LVTH373FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2003, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SN54LVTH373 ...J OR W PACKAGE SN74LVTH373 . . . DB, DW, NS, OR PW PACKAGE (TOP VIEW) SN54LVTH373 . . . FK PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE 3 2 1 20 19 9 10 11 12 13 4 5 6 7 8 18 17 16 15 14 2D 2Q 3Q 3D 4D 8D 7D 7Q 6Q 6D On products compliant to MILPRF38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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