PEEL22LV10AZPI-35 datasheet(4/10 Pages) ETC2

Part #	PEEL22LV10AZPI-35

Description	CMOS Programmable Electrically Erasable Logic Device

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PEEL

TM 22LV10AZ

04-02-037D

Programmable I/O Macrocell

The

unique

twelve-configuration

output

macrocell

provides complete control over the architecture of each

output.

The

ability

to

configure

each

output

independently lets you to tailor the configuration of the

PEEL22LV10AZ to the precise requirements of your

design.

Macrocell Architecture

Each I/O macrocell, as shown in Figure 4, consists of a

D-type flip-flop and two signal-select multiplexers. The

configuration of each macrocell is determined by the

four EEPROM bits controlling these multiplexers. These

bits determine output polarity, output type (registered or

non-registered) and input-feedback path (bidirectional

I/O, combinatorial feedback). Refer to Table 1 for

details.

Equivalent

circuits

for

the

twelve

macrocell

configurations are illustrated in Figure 6. In addition to

emulating

the

four

PAL-type

output

structures

(configurations 3, 4, 9, and 10), the macrocell provides

eight additional configurations. When creating a PEEL

device design, the desired macrocell configuration is

generally specified explicitly in the design file. When the

design is

assembled or

compiled,

the

macrocell

configuration bits are defined in the last lines of the

JEDEC programming file.

Output Type

The signal from the OR array can be fed directly to the

output pin (combinatorial function) or latched in the D-

type flip-flop (registered function). The D-type flip-flop

latches data on the rising edge of the clock and is

controlled by the global preset and clear terms. When

the synchronous preset term is satisfied, the Q output of

the register is set HIGH at the next rising edge of the

clock input. Satisfying the asynchronous clear sets Q

LOW, regardless of the clock state. If both terms are

satisfied simultaneously, the clear will override the

preset.

Output Polarity

Each macrocell can be configured to implement active-

high

or

active-low

logic.

Programmable

polarity

eliminates the need for external inverters.

Output Enable

The output of each I/O macrocell can be enabled or

disabled

under

the

control

of

its

associated

programmable output enable product term. When the

logical conditions programmed on the output enable

term are satisfied, the output signal is propagated to the

I/O pin. Otherwise, the output buffer is switched into the

high-impedance state.

Under the control of the output enable term, the I/O pin

can function as a dedicated input, a dedicated output,

or a bi-directional I/O. Opening every connection on the

output enable term will permanently enable the output

buffer and yield a dedicated output. Conversely, if every

connection is intact, the enable term will always be

logically false and the I/O will function as a dedicated

input.

Input/Feedback Select

The PEEL22LV10AZ macrocell also provides control

over the feedback path. The input/feedback signal

associated with each I/O macrocell can be obtained

from three different locations; from the I/O input pin,

from the Q output of the flip-flop (registered feedback),

or directly from the OR gate (combinatorial feedback).

Bi-directional I/O

The input/feedback signal is taken from the I/O pin

when using the pin as a dedicated input or as a bi-

directional I/O. (Note that it is possible to create a

registered output function with a bi-directional I/O, refer

to Figure 4.

Figure 4 - Block Diagram of the PEEL22LV10AZ I/O

Macrocell

Combinatorial Feedback

The signal-select multiplexer gives the macrocell the

ability to feedback the output of the OR gate, bypassing

the output buffer, regardless of whether the output

function is registered or combinatorial. This feature

allows the creation of asynchronous latches, even when

the output must be disabled. (Refer to configurations 5,

6, 7, and 8 in Figure 6.)

Registered Feedback

Feedback

also

can

be

taken from

the

register,

regardless

of

whether

the

output

function

is

programmed to be combinatorial or registered. When

implementing

a

combinatorial

output

function,

registered feedback allows for the internal latching of

states without giving up the use of the external output.

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