TPS360633

BATTERY BACKUP SUPERVISOR FOR LOW POWER PROCESSORS

SLVS335C − DECEMBER 2000 − REVISED JANUARY 2007

8

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOUT = 2 V,

IOH = −400 µA

VOUT − 0.2 V

VOH

High-level output voltage

RESET

VOUT = 3.3 V IOH = −2 mA

VOUT = 5 V,

IOH = −3 mA

VOUT − 0.4 V

V

VOH

High-level output voltage

VOUT = 1.8 V, IOH = −20 µA

VOUT − 0.3 V

V

PFO

VOUT = 3.3 V, IOH = −80 µA

VOUT = 5 V,

IOH = −120 µA

VOUT − 0.4 V

RESET

VOUT = 2 V,

IOL = 400 µA

0.2

VOL

Low-level output voltage

RESET

PFO

VOUT = 3.3 V, IOL = 2 mA

VOUT = 5 V,

IOL = 3 mA

0.4

V

Vres

Power-up reset voltage (see Note 2)

VBAT > 1.1 V or

VDD > 1.4 V, IOL = 20 µA

0.4

V

IO = 5 mA,

VDD = 1.8 V

VDD − 50 mV

Normal mode

IO = 75 mA,

VDD = 3.3 V

VDD − 150 mV

VOUT

Normal mode

IO = 150 mA, VDD = 5 V

VDD − 250 mV

V

VOUT

Battery-backup mode

IO = 4 mA,

VBAT = 1.5 V

VBAT − 50 mV

V

Battery-backup mode

IO = 75 mA,

VBAT = 3.3 V

VBAT − 150 mV

rds(on)

VDD to VOUT on-resistance

VDD = 3.3 V

1

2

Ω

rds(on)

VBAT to VOUT on-resistance

VBAT = 3.3 V

1

2

Ω

VIT

Negative-going input

threshold voltage

(see Notes 3 and 4)

TPS3606x33

2.87

2.93

2.99

V

V(PFI)

Power-fail input

threshold voltage

PFI

1.13

1.15

1.17

V(SWN)

Battery switch threshold voltage

negative-going VOUT

VIT + 1% VIT + 2%

VIT + 3.2%

V

NOTES:

2. The lowest supply voltage at which RESET becomes active. tr(VDD) ≥ 15 µs/V.

3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1

µF) should be placed near the supply terminal.

4. Voltage is sensed at VOUT

5. For details on how to optimize current consumption when using WDI refer to section detailed description.

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