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OPA2734AIDGST Datasheet(PDF) 8 Page - Burr-Brown (TI) |
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OPA2734AIDGST Datasheet(HTML) 8 Page - Burr-Brown (TI) |
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8 / 23 page  OPA734, OPA2734 OPA735, OPA2735 SBOS282B − DECEMBER 2003 − REVISED FEBRUARY 2005 www.ti.com 8 APPLICATIONS INFORMATION The OPA734 and OPA735 series of op amps are unity-gain stable and free from unexpected output phase reversal. They use auto-zeroing techniques to provide low offset voltage and demonstrate very low drift over time and temperature. Good layout practice mandates the use of a 0.1 µF capacitor placed closely across the supply pins. For lowest offset voltage and precision performance, circuit layout and mechanical conditions should be optimized. Avoid temperature gradients that create thermoelectric (Seebeck) effects in thermocouple junctions formed from connecting dissimilar conductors. These thermally-generated potentials can be made to cancel by assuring that they are equal on both input terminals: 1. Use low thermoelectric-coefficient connections (avoid dissimilar metals). 2. Thermally isolate components from power supplies or other heat sources. 3. Shield op amp and input circuitry from air currents such as cooling fans. Following these guidelines will reduce the likelihood of junctions being at different temperatures, which can cause thermoelectric voltages of 0.1 µV/°C or higher, depending on the materials used. OPERATING VOLTAGE The OPA734 and OPA735 op amp family operates with a power-supply range of +2.7V to +12V ( ±1.35V to ±6V). Supply voltages higher than +13.2V (absolute maximum) can permanently damage the amplifier. Parameters that vary over supply voltage or temperature are shown in the Typical Characteristics section of this data sheet. OPA734 ENABLE FUNCTION The enable/shutdown digital input is referenced to the V− supply voltage of the op amp. A logic HIGH enables the op amp. A valid logic HIGH is defined as > (V−) + 2V. The valid logic HIGH signal can be up to the positive supply, independent of the negative power supply voltage. A valid logic LOW is defined as < 0.8V above the V− supply pin. If dual or split power supplies are used, be sure that logic input signals are properly referred to the negative supply voltage. The Enable pin is connected to internal pull-up circuitry and will enable the device if this pin is left open circuit. The logic input is a CMOS input. Separate logic inputs are provided for each op amp on the dual version. For battery-operated applications, this feature can be used to greatly reduce the average current and extend battery life. The enable time is 150 µs, which includes one full auto-zero cycle required by the amplifier to return to VOS accuracy. Prior to returning to full accuracy, the amplifier may function properly, but with unspecified offset voltage. Disable time is 1.5 µs. When disabled, the output assumes a high-impedance state. The disable state allows the OPA734 to be operated as a gated amplifier, or to have the output multiplexed onto a common analog output bus. INPUT VOLTAGE The input common-mode range extends from (V−) − 0.1V to (V+) − 1.5V. For normal operation, the inputs must be limited to this range. The common-mode rejection ratio is only valid within the specified input common-mode range. A lower supply voltage results in lower input common- mode range; therefore, attention to these values must be given when selecting the input bias voltage. For example, when operating on a single 3V power supply, common- mode range is from 0.1V below ground to half the power-supply voltage. Normally, input bias current is approximately 100pA; however, input voltages exceeding the power supplies can cause excessive current to flow in or out of the input pins. Momentary voltages greater than the power supply can be tolerated if the input current is limited to 10mA. This is easily accomplished with an input resistor, as shown in Figure 1. 50 Ω OPA735 +5V V IN V OUT 10mA max I OVERLOAD Current−limited resistor required if input voltage exceeds supply rails by ≥ 0.5V. Figure 1. Input Current Protection INTERNAL OFFSET CORRECTION The OPA734 and OPA735 series of op amps use an auto-zero topology with a time-continuous 1.6MHz op amp in the signal path. This amplifier is zero-corrected every 100 µs using a proprietary technique. Upon power-up, the amplifier requires one full auto-zero cycle of approximately 100 µs in addition to the start-up time for the bias circuitry to achieve specified VOS accuracy. Prior to this time, the amplifier may function properly but with unspecified offset voltage. |
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