Doc # 14-02-045 Rev A ECN 01-1118

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The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

NanoAmp Solutions, Inc.

NT5DS4M32EG

Advance Information

Burst Interruption

Read Interrupted by Read

Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the

previous burst is interrupted, the remaining address are overridden by the new address with the full burst length. The

data from the previous Read command continues to appear on the outputs until the /CAS latency from the interrupting

Read command is satisfied. Read to Read interval is minimum 1 tCK.

Figure 10: Burst Interrupted by Read (Burst length = 4, /CAS Latency = 3)

Read Interrupted by Burst stop & Write

To interrupt Burst Read with a write command, Burst stop command must be asserted to avoid data contention on

the I/O bus by placing the DQ’s(Output drivers) in a high impedance state at least one clock cycle before the Write

Command is initiated. Once the burst stop command has been issued, the minimum delay to a write command is

CL(RU). [CL is /CAS Latency and RU means round up to the nearest integer.]

012

READ B

/CK

CK

Command

345

6

7

8

NOP

NOP

NOP

NOP

NOP

NOP

NOP

READ A

DQS

Douta0 Douta1 Doutb0 Doutb1

DQ’s

Doutb2 Doutb3

/CAS Latency = 3

012

READ B

/CK

CK

Command

345

6

7

8

NOP

NOP

NOP

NOP

NOP

NOP

NOP

READ A

DQS

Douta0 Douta1 Doutb0 Doutb1

DQ’s

Doutb2 Doutb3

/CAS Latency = 3

012

Burst

stop

/CK

CK

Command

345

6

7

8

NOP

NOP

NOP

WRITE

NOP

NOP

READ

DQS

Dout0 Dout1

Din 0

Din 1

DQ’s

Din 2

Din 3

/CAS Latency = 3

Preamble

012

Burst

stop

/CK

CK

Command

345

6

7

8

NOP

NOP

NOP

WRITE

NOP

NOP

READ

DQS

Dout0 Dout1

Din 0

Din 1

DQ’s

Din 2

Din 3

/CAS Latency = 3

Preamble