www.ti.com

CLOCK

CONVST

12ns

Cyc e

l 1

Cyc e

l 2

A

B

C

12ns

TBD

TBD

TIMING REQUIREMENTS

(1)

ADS7863

SBAS383 – JUNE 2007

TIMING CHARACTERISTICS (continued)

NOTE: All CONVST commands that occur more than 12ns before the rising edge of cycle ‘1’ of the external clock

(Region ‘A’) initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands that occur TBDns after the

rising edge of cycle ‘1’ or 12ns before the rising edge of cycle 2 (Region ‘B’) initiate a conversion on the rising edge

of cycle ‘2’. All CONVST commands that occur TBDns after the rising edge of cycle ‘2’ (Region ‘C’) initiate a

conversion on the rising edge of the next clock period.

The CONVST pin should never be switched from LOW to HIGH in the region 12ns prior to the rising edge of the

CLOCK and TBDns after the rising edge (gray areas). If CONVST is toggled in this gray area, the conversion could

begin on either the same rising edge of the CLOCK or the following edge.

Figure 2. CONVST Timing

Over recommended operating free-air temperature range at –40

°C to +125°C, AV

otherwise noted.

ADS7863

SYMBOL

PARAMETER

COMMENTS

MIN

MAX

UNIT

Conversion time

541.67

ns

Acquisition time

125

ns

CLOCK frequency

See Figure 1

1

24

MHz

CLOCK period

See Figure 1

41.67

1000

ns

CLOCK low time

See Figure 1

5

ns

CLOCK high time

See Figure 1

5

ns

CONVST high time

See Figure 1

15

ns

SDI setup time to CLOCK falling edge

See Figure 1

10

ns

SDI hold time to CLOCK falling edge

See Figure 1

5

ns

RD high setup time to CLOCK falling edge

See Figure 1

10

ns

RD high hold time to CLOCK falling edge

See Figure 1

5

ns

CONVST low time

See Figure 1

15

ns

RD low time relative to CLOCK falling edge

See Figure 1

15

ns

CS low to SDOx valid

See Figure 1

20

ns

SDOx data setup time to CLOCK falling

See Figure 1

25

ns

edge

SDOx data hold time to CLOCK falling edge

See Figure 1

5

ns

CONVST setup time to rising edge of

See Figure 1

12

ns

CLOCK

CLOCK rising edge to BUSY low delay

See Figure 1

3

ns

CS low to RD high delay

See Figure 1

10

ns

(1)

8

Submit Documentation Feedback