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TDA9901TS Datasheet(PDF) 8 Page - NXP Semiconductors |
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TDA9901TS Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 20 page  1999 Oct 08 8 Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier TDA9901 Io(CMADC)(max) maximum output current − 1.0 − mA Co(CMADC) output capacitance − 3 − pF Reference voltage output VGA: pin CMVGA Vref(CMVGA) VGA reference output voltage referenced to VDDA; Tamb =25 °C VDDA − 2.48 VDDA − 2.30 VDDA − 2.17 V Ro(CMVGA) output resistance Tamb =25 °C − 920 Ω ∆Vref(CMVGA)/∆T VGA reference output voltage variation with temperature − 1.75 − mV/ °C Io(CMVGA)(max) maximum output current − 1.0 − mA Co(CMVGA) output capacitance − 3 − pF Gain switching characteristics (in latched mode); fCLK = 52 MHz; Tamb =25°C; (see Fig.3) th input data hold time 2.0 −− ns tsu input data set-up time 3.8 −− ns tW input data pulse width 5.8 −− ns tPD1 propagation delay time − 4.2 5.9 ns tset1 gain settling time 10 to 90% full scale if ±6 dB gain change; note 3 − 2.6 3.2 ns Gain switching characteristics (in transparent mode); fCLK = 52 MHz; Tamb =25°C; (see Fig.4) tPD2 propagation delay time − 6.7 9.5 ns tset2 gain settling time 10 to 90% full scale if ±6 dB gain change; note 4 − 5.4 6.9 ns Clock timing input: pins CLK and CLKN (see Fig.3) fCLK(max) maximum clock frequency 52 −− MHz tCPL clock LOW pulse width 4.0 −− ns tCPH clock HIGH pulse width 4.0 −− ns tr rise time − 4 − ns tf fall time − 4 − ns Digital inputs: pins TE, GRAY0, GRAY1 and GRAY2 VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2.0 − VDDD V IIH HIGH-level input current −10 − +10 µA IIL LOW-level input current −10 − +10 µA Ci input capacitance −− 3pF Clock inputs in TTL mode VIL LOW-level input voltage note 5 0 − 0.8 V VIH HIGH-level input voltage note 5 2.0 − VDDD V IIH HIGH-level input current 15 − 80 µA IIL LOW-level input current −40 −−10 µA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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